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AMD PISTACHIO mainboard support. 

The following ACPI features are supported:
 1. S1, S4, S5 sleep and wake up (by power button).
 2. Thermal configuration based on ADT7475.
 3. HPET timer.
 4. Interrupt routing based on ACPI table.

Signed-off-by: Maggie Li <maggie.li@amd.com>
Reviewed-by: Michael Xie <michael.xie@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Maggie Li 2008-12-09 21:52:42 +00:00 committed by Carl-Daniel Hailfinger
parent 8b643cea5a
commit 19ead962c4
24 changed files with 6126 additions and 0 deletions
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274
src/mainboard/amd/pistachio/Config.lb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
##
##
##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
default ROM_SECTION_OFFSET = 0
end
##
## Compute the start location and size size of
## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
#dir /drivers/si/3114
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE
object get_bus_conf.o
object irq_tables.o
end
if HAVE_ACPI_TABLES
object acpi_tables.o
object fadt.o
makerule dsdt.c
depends "$(MAINBOARD)/acpi/*.asl"
action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
action "mv dsdt.hex dsdt.c"
end
object ./dsdt.o
end
#object reset.o
if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end
else
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -g -dA -fverbose-asm -c -S -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
end
#The variables belong to mainboard are defined here.
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
#Define gfx_dual_slot, 0: single slot, 1: dual slot
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
#Define gfx_tmds, 0: didn't support TMDS, 1: support
#Define gfx_compliance, 0: didn't support compliance, 1: support
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
chip cpu/amd/socket_AM2
device apic 0 on end
end
end
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on # southbridge, K8 HT Configuration
chip southbridge/amd/rs690
device pci 0.0 on end # HT 0x7910
# device pci 0.1 off end # CLK
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard
device pci 5.0 on end # Internal Graphics 0x791F
register "rom_address" = "0xfff00000"
end
end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
device pci 3.0 off end # PCIE P2P bridge 0x791b
device pci 4.0 on end # PCIE P2P bridge 0x1914
device pci 5.0 on end # PCIE P2P bridge 0x7915
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
register "vga_rom_address" = "0xfff00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"
register "gfx_dual_slot" = "0"
register "gfx_lane_reversal" = "0"
register "gfx_tmds" = "0"
register "gfx_compliance" = "0"
register "gfx_reconfiguration" = "1"
register "gfx_link_width" = "0"
end
chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
device pci 12.0 on end # SATA 0x4380
device pci 13.0 on end # USB 0x4387
device pci 13.1 on end # USB 0x4388
device pci 13.2 on end # USB 0x4389
device pci 13.3 on end # USB 0x438a
device pci 13.4 on end # USB 0x438b
device pci 13.5 on end # USB 2 0x4386
device pci 14.0 on # SM 0x4385
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 off end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 off end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 off end
end
end # SM
device pci 14.1 on end # IDE 0x438c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on end # LPC 0x438d
device pci 14.4 on end # PCI 0x4384
device pci 14.5 on end # ACI 0x4382
device pci 14.6 on end # MCI 0x438e
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "hda_viddid" = "0x10ec0882"
end #southbridge/amd/sb600
end # device pci 18.0
device pci 18.1 on end # K8 Address Map
device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode
device pci 18.3 on end # K8 Miscellaneous Control
end #northbridge/amd/amdk8
end #pci_domain
end #northbridge/amd/amdk8/root_complex

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src/mainboard/amd/pistachio/Options.lb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
##
##
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses HAVE_ACPI_TABLES
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_USE_PRINTK_IN_CAR
uses CONFIG_VIDEO_MB
uses CONFIG_GFXUMA
###
### Build options
###
##
## ROM_SIZE is the size of boot ROM that this board will use.
##
default ROM_SIZE=524288
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
#default FALLBACK_SIZE=131072
#256K
default FALLBACK_SIZE=0x40000
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=11
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1
## ACPI tables will be included
default HAVE_ACPI_TABLES=1
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=0
##
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=2
default CONFIG_MAX_PHYSICAL_CPUS=1
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
# BTDC: Only one HT device on Herring.
#HT Unit ID offset
#default HT_CHAIN_UNITID_BASE=0x6
default HT_CHAIN_UNITID_BASE=0x0
#real SB Unit ID
default HT_CHAIN_END_UNITID_BASE=0x1
#make the SB HT chain on bus 0
default SB_HT_CHAIN_ON_BUS0=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xc8000
default DCACHE_RAM_SIZE=0x8000
default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="pistachio"
default MAINBOARD_VENDOR="amd"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
##
## coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000
##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD = 1
###
### Defaults of options that you may want to override in the target config file
###
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
default CONFIG_USE_PRINTK_IN_CAR=1
##
## The Serial Console
##
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200
# Select the serial console base port
default TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
##
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## CRIT 3 critical conditions
## ERR 4 error conditions
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
default CONFIG_VIDEO_MB=1
default CONFIG_GFXUMA=1
### End Options.lb
end

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src/mainboard/amd/pistachio/acpi/cpstate.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file defines the processor and performance state capability
* for each core in the system. It is included into the DSDT for each
* core. It assumes that each core of the system has the same performance
* characteristics.
*/
/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
{
Scope (\_PR) {
Processor(CPU0,0,0x808,0x06) {
Include ("cpstate.asl")
}
Processor(CPU1,1,0x0,0x0) {
Include ("cpstate.asl")
}
Processor(CPU2,2,0x0,0x0) {
Include ("cpstate.asl")
}
Processor(CPU3,3,0x0,0x0) {
Include ("cpstate.asl")
}
}
*/
/*
* 1. Get the CPUID to know what the version of the CPU is. (or see what powernow
* reports)
* 2. Find how many P-states the CPU supports, power and frequecy in each
* P-states in 'Power and Thermal Data Sheet.' (PTDS)
* 3. Go to BIOS and Kernel Developer's Guide (BKDG) and find Low FID Frequency
* Table & High FID Frequency Table. Find Fid for each frequency.
* 4. In PTDS, got the Voltage for each P-state. In table VID Code Voltages of BKDG,
* find the VID for each Voltage.
* Is that clear?
*/
/* P-state support: The maximum number of P-states supported by the */
/* CPUs we'll use is 6. */
Name(_PSS, Package(){
/* The processor core clock PLL lock time is 2 us for AMD NPT Family 0Fh Processors.*/
/* vst=100us*/
/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x13<<6|0xD, 0x13<<6|0xD */
/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x14<<6|0xC, 0x14<<6|0xC */
/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x15<<6|0xA, 0x15<<6|0xA */
/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x16<<6|0x8, 0x16<<6|0x8 */
/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x1E<<6|0x0, 0x1E<<6|0x0 */
/*
* Package() {2100, 35000, 100, 7, 0xE8202CCD, 0x04CD},
* Package() {2000, 30100, 100, 7, 0xE8202D0C, 0x050C},
* Package() {1800, 26400, 100, 7, 0xE8202D4A, 0x054A},
* Package() {1600, 23000, 100, 7, 0xE8202D88, 0x0588},
* Package() { 800, 9400, 100, 7, 0xE8202F80, 0x0780},
*/
/*Use this tricky method to reserve 8 Pstates space*/
Package() {0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF},
Package() {0x7FFFFFFF, 0x8FFFFFFF, 0x9FFFFFFF, 0xAFFFFFFF, 0xBFFFFFFF, 0xCFFFFFFF},
Package() {0xDFFFFFFF, 0xEFFFFFFF, 0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF},
Package() {0x5FFFFFFF, 0x6FFFFFFF, 0x7FFFFFFF, 0x8FFFFFFF, 0x9FFFFFFF, 0xAFFFFFFF},
Package() {0xBFFFFFFF, 0xCFFFFFFF, 0xDFFFFFFF, 0xEFFFFFFF, 0x1FFFFFFF, 0x2FFFFFFF},
Package() {0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF, 0x7FFFFFFF, 0x8FFFFFFF},
Package() {0x9FFFFFFF, 0xAFFFFFFF, 0xBFFFFFFF, 0xCFFFFFFF, 0xDFFFFFFF, 0xEFFFFFFF},
Package() {0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF},
})
Name(_PCT, Package(){
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
})
Method(_PPC, 0){
Return(0)
}

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src/mainboard/amd/pistachio/acpi/debug.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
DefinitionBlock (
"DSDT.AML",
"DSDT",
0x01,
"XXXXXX",
"XXXXXXXX",
0x00010001
)
{
Include ("debug.asl")
}
*/
/*
* 0x80: POST_BASE
* 0x3F8: DEBCOM_BASE
* X80: POST_REGION
* P80: PORT80
*
* CREG: DEBCOM_REGION
* CUAR: DEBCOM_UART
* CDAT: DEBCOM_DATA
* CDLM: DEBCOM_DLM
* DLCR: DEBCOM_LCR
* CMCR: DEBCOM_MCR
* CLSR: DEBCOM_LSR
*
* DEBUG_INIT DINI
*/
OperationRegion(X80, SystemIO, 0x80, 1)
Field(X80, ByteAcc, NoLock, Preserve)
{
P80, 8
}
OperationRegion(CREG, SystemIO, 0x3F8, 8)
Field(CREG, ByteAcc, NoLock, Preserve)
{
CDAT, 8,
CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8
}
/*
* DINI
* Initialize the COM port to 115,200 8-N-1
*/
Method(DINI)
{
store(0x83, DLCR)
store(0x01, CDAT) /* 115200 baud (low) */
store(0x00, CDLM) /* 115200 baud (high) */
store(0x03, DLCR) /* word=8 stop=1 parity=none */
store(0x03, CMCR) /* DTR=1 RTS=1 Out2=Off Loop=Off */
store(0x00, CDLM) /* turn off interrupts */
}
/*
* THRE
* Wait for COM port transmitter holding register to go empty
*/
Method(THRE)
{
and(CLSR, 0x20, local0)
while (Lequal(local0, Zero)) {
and(CLSR, 0x20, local0)
}
}
/*
* OUTX
* Send a single raw character
*/
Method(OUTX, 1)
{
THRE()
store(Arg0, CDAT)
}
/*
* OUTC
* Send a single character, expanding LF into CR/LF
*/
Method(OUTC, 1)
{
if (LEqual(Arg0, 0x0a)) {
OUTX(0x0d)
}
OUTX(Arg0)
}
/*
* DBGN
* Send a single hex nibble
*/
Method(DBGN, 1)
{
and(Arg0, 0x0f, Local0)
if (LLess(Local0, 10)) {
add(Local0, 0x30, Local0)
} else {
add(Local0, 0x37, Local0)
}
OUTC(Local0)
}
/*
* DBGB
* Send a hex byte
*/
Method(DBGB, 1)
{
ShiftRight(Arg0, 4, Local0)
DBGN(Local0)
DBGN(Arg0)
}
/*
* DBGW
* Send a hex word
*/
Method(DBGW, 1)
{
ShiftRight(Arg0, 8, Local0)
DBGB(Local0)
DBGB(Arg0)
}
/*
* DBGD
* Send a hex Dword
*/
Method(DBGD, 1)
{
ShiftRight(Arg0, 16, Local0)
DBGW(Local0)
DBGW(Arg0)
}
/*
* DBGO
* Send either a string or an integer
*/
Method(DBGO, 1)
{
/* DINI() */
if (LEqual(ObjectType(Arg0), 1)) {
if (LGreater(Arg0, 0xffff)) {
DBGD(Arg0)
} else {
if (LGreater(Arg0, 0xff)) {
DBGW(Arg0)
} else {
DBGB(Arg0)
}
}
} else {
Name(BDBG, Buffer(80) {})
store(Arg0, BDBG)
store(0, Local1)
while (One) {
store(GETC(BDBG, Local1), Local0)
if (LEqual(Local0, 0)) {
return (0)
}
OUTC(Local0)
Increment(Local1)
}
}
return (0)
}
/* Get a char from a string */
Method(GETC, 2)
{
CreateByteField(Arg0, Arg1, DBGC)
return (DBGC)
}

3
src/mainboard/amd/pistachio/acpi/doit.sh Normal file
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#!/bin/bash
#cpp -P dsdt.asl > dsdt.i
iasl dsdt.asl

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src/mainboard/amd/pistachio/acpi/dsdt.asl Normal file
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118
src/mainboard/amd/pistachio/acpi/globutil.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
Scope(\_SB) {
Include ("globutil.asl")
}
*/
/* string compare functions */
Method(MIN, 2)
{
if (LLess(Arg0, Arg1)) {
Return(Arg0)
} else {
Return(Arg1)
}
}
Method(SLEN, 1)
{
Store(Arg0, Local0)
Return(Sizeof(Local0))
}
Method(S2BF, 1)
{
Add(SLEN(Arg0), One, Local0)
Name(BUFF, Buffer(Local0) {})
Store(Arg0, BUFF)
Return(BUFF)
}
/* Strong string compare. Checks both length and content */
Method(SCMP, 2)
{
Store(S2BF(Arg0), Local0)
Store(S2BF(Arg1), Local1)
Store(Zero, Local4)
Store(SLEN(Arg0), Local5)
Store(SLEN(Arg1), Local6)
Store(MIN(Local5, Local6), Local7)
While(LLess(Local4, Local7)) {
Store(Derefof(Index(Local0, Local4)), Local2)
Store(Derefof(Index(Local1, Local4)), Local3)
if (LGreater(Local2, Local3)) {
Return(One)
} else {
if (LLess(Local2, Local3)) {
Return(Ones)
}
}
Increment(Local4)
}
if (LLess(Local4, Local5)) {
Return(One)
} else {
if (LLess(Local4, Local6)) {
Return(Ones)
} else {
Return(Zero)
}
}
}
/* Weak string compare. Checks to find Arg1 at beginning of Arg0.
* Fails if length(Arg0) < length(Arg1). Returns 0 on Fail, 1 on
* Pass.
*/
Method(WCMP, 2)
{
Store(S2BF(Arg0), Local0)
Store(S2BF(Arg1), Local1)
if (LLess(SLEN(Arg0), SLEN(Arg1))) {
Return(0)
}
Store(Zero, Local2)
Store(SLEN(Arg1), Local3)
While(LLess(Local2, Local3)) {
if (LNotEqual(Derefof(Index(Local0, Local2)),
Derefof(Index(Local1, Local2)))) {
Return(0)
}
Increment(Local2)
}
Return(One)
}
/* ARG0 = IRQ Number(0-15)
* Returns Bit Map
*/
Method(I2BM, 1)
{
Store(0, Local0)
if (LNotEqual(ARG0, 0)) {
Store(1, Local1)
ShiftLeft(Local1, ARG0, Local0)
}
Return(Local0)
}

244
src/mainboard/amd/pistachio/acpi/ide.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
Scope (_SB) {
Device(PCI0) {
Device(IDEC) {
Name(_ADR, 0x00140001)
Include ("ide.asl")
}
}
}
*/
/* Some timing tables */
Name(UDTT, Package(){ /* Udma timing table */
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
})
Name(MDTT, Package(){ /* MWDma timing table */
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
})
Name(POTT, Package(){ /* Pio timing table */
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
})
/* Some timing register value tables */
Name(MDRT, Package(){ /* MWDma timing register table */
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
})
Name(PORT, Package(){
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
})
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
Field(ICRG, AnyAcc, NoLock, Preserve)
{
PPTS, 8, /* Primary PIO Slave Timing */
PPTM, 8, /* Primary PIO Master Timing */
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
PMTM, 8, /* Primary MWDMA Master Timing */
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
PPSM, 4, /* Primary PIO slave Mode */
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
PDSM, 4, /* Primary UltraDMA Mode */
}
Method(GTTM, 1) /* get total time*/
{
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
Increment(Local0)
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
Increment(Local1)
Return(Multiply(30, Add(Local0, Local1)))
}
Device(PRID)
{
Name (_ADR, Zero)
Method(_GTM, 0)
{
NAME(OTBF, Buffer(20) { /* out buffer */
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
})
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
/* Just return if the channel is disabled */
If(And(PPCR, 0x01)) { /* primary PIO control */
Return(OTBF)
}
/* Always tell them independent timing available and IOChannelReady used on both drives */
Or(BFFG, 0x1A, BFFG)
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
Or(BFFG, 0x01, BFFG)
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
}
Else {
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
}
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
Or(BFFG, 0x04, BFFG)
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
}
Else {
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
}
Return(OTBF) /* out buffer */
} /* End Method(_GTM) */
Method(_STM, 3, NotSerialized)
{
NAME(INBF, Buffer(20) { /* in buffer */
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
})
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
Divide(Local0, 7, PDMM,)
Or(PDCR, 0x01, PDCR)
}
Else {
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
Store(DerefOf(Index(MDRT, Local0)), PMTM)
}
}
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
Divide(Local0, 7, PDSM,)
Or(PDCR, 0x02, PDCR)
}
Else {
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
Store(DerefOf(Index(MDRT, Local0)), PMTS)
}
}
/* Return(INBF) */
} /*End Method(_STM) */
Device(MST)
{
Name(_ADR, 0)
Method(_GTF) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
})
CreateByteField(CMBF, 1, POMD)
CreateByteField(CMBF, 8, DMMD)
CreateByteField(CMBF, 5, CMDA)
CreateByteField(CMBF, 12, CMDB)
CreateByteField(CMBF, 19, CMDC)
Store(0xA0, CMDA)
Store(0xA0, CMDB)
Store(0xA0, CMDC)
Or(PPMM, 0x08, POMD)
If(And(PDCR, 0x01)) {
Or(PDMM, 0x40, DMMD)
}
Else {
Store(Match
(MDTT, MLE, GTTM(PMTM),
MTR, 0, 0), Local0)
If(LLess(Local0, 3)) {
Or(0x20, Local0, DMMD)
}
}
Return(CMBF)
}
} /* End Device(MST) */
Device(SLAV)
{
Name(_ADR, 1)
Method(_GTF) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
})
CreateByteField(CMBF, 1, POMD)
CreateByteField(CMBF, 8, DMMD)
CreateByteField(CMBF, 5, CMDA)
CreateByteField(CMBF, 12, CMDB)
CreateByteField(CMBF, 19, CMDC)
Store(0xB0, CMDA)
Store(0xB0, CMDB)
Store(0xB0, CMDC)
Or(PPSM, 0x08, POMD)
If(And(PDCR, 0x02)) {
Or(PDSM, 0x40, DMMD)
}
Else {
Store(Match
(MDTT, MLE, GTTM(PMTS),
MTR, 0, 0), Local0)
If(LLess(Local0, 3)) {
Or(0x20, Local0, DMMD)
}
}
Return(CMBF)
}
} /* End Device(SLAV) */
}

258
src/mainboard/amd/pistachio/acpi/routing.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
Include ("routing.asl")
}
*/
/* Routing is in System Bus scope */
Scope(\_SB) {
Name(PR0, Package(){
/* NB devices */
/* Bus 0, Dev 0 - RS690 Host Controller */
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 },
Package(){0x0002FFFF, 2, INTA, 0 },
Package(){0x0002FFFF, 3, INTB, 0 },
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
Package(){0x0004FFFF, 0, INTA, 0 },
Package(){0x0004FFFF, 1, INTB, 0 },
Package(){0x0004FFFF, 2, INTC, 0 },
Package(){0x0004FFFF, 3, INTD, 0 },
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
Package(){0x0006FFFF, 0, INTC, 0 },
Package(){0x0006FFFF, 1, INTD, 0 },
Package(){0x0006FFFF, 2, INTA, 0 },
Package(){0x0006FFFF, 3, INTB, 0 },
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
Package(){0x0007FFFF, 0, INTD, 0 },
Package(){0x0007FFFF, 1, INTA, 0 },
Package(){0x0007FFFF, 2, INTB, 0 },
Package(){0x0007FFFF, 3, INTC, 0 },
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
/* SB devices */
/* Bus 0, Dev 17 - SATA controller #2 */
/* Bus 0, Dev 18 - SATA controller #1 */
Package(){0x0012FFFF, 1, INTA, 0 },
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
Package(){0x0013FFFF, 0, INTA, 0 },
Package(){0x0013FFFF, 1, INTB, 0 },
Package(){0x0013FFFF, 2, INTC, 0 },
Package(){0x0013FFFF, 3, INTD, 0 },
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
Package(){0x0014FFFF, 0, INTA, 0 },
Package(){0x0014FFFF, 1, INTB, 0 },
Package(){0x0014FFFF, 2, INTC, 0 },
Package(){0x0014FFFF, 3, INTD, 0 },
})
Name(APR0, Package(){
/* NB devices in APIC mode */
/* Bus 0, Dev 0 - RS690 Host Controller */
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },
/* Package(){0x0002FFFF, 1, 0, 19 }, */
/* Package(){0x0002FFFF, 2, 0, 16 }, */
/* Package(){0x0002FFFF, 3, 0, 17 }, */
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
Package(){0x0003FFFF, 0, 0, 19 },
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
Package(){0x0004FFFF, 0, 0, 16 },
/* Package(){0x0004FFFF, 1, 0, 17 }, */
/* Package(){0x0004FFFF, 2, 0, 18 }, */
/* Package(){0x0004FFFF, 3, 0, 19 }, */
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
Package(){0x0005FFFF, 0, 0, 17 },
/* Package(){0x0005FFFF, 1, 0, 18 }, */
/* Package(){0x0005FFFF, 2, 0, 19 }, */
/* Package(){0x0005FFFF, 3, 0, 16 }, */
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
Package(){0x0006FFFF, 0, 0, 18 },
/* Package(){0x0006FFFF, 1, 0, 19 }, */
/* Package(){0x0006FFFF, 2, 0, 16 }, */
/* Package(){0x0006FFFF, 3, 0, 17 }, */
/* Bus 0, Dev 7 - PCIe Bridge for network card */
Package(){0x0007FFFF, 0, 0, 19 },
/* Package(){0x0007FFFF, 1, 0, 16 }, */
/* Package(){0x0007FFFF, 2, 0, 17 }, */
/* Package(){0x0007FFFF, 3, 0, 18 }, */
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
/* SB devices in APIC mode */
/* Bus 0, Dev 17 - SATA controller #2 */
/* Bus 0, Dev 18 - SATA controller #1 */
Package(){0x0012FFFF, 0, 0, 22 },
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
Package(){0x0013FFFF, 0, 0, 16 },
Package(){0x0013FFFF, 1, 0, 17 },
Package(){0x0013FFFF, 2, 0, 18 },
Package(){0x0013FFFF, 3, 0, 19 },
/* Package(){0x00130004, 2, 0, 18 }, */
/* Package(){0x00130005, 3, 0, 19 }, */
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
Package(){0x0014FFFF, 0, 0, 16 },
Package(){0x0014FFFF, 1, 0, 17 },
Package(){0x0014FFFF, 2, 0, 18 },
Package(){0x0014FFFF, 3, 0, 19 },
/* Package(){0x00140004, 2, 0, 18 }, */
/* Package(){0x00140004, 3, 0, 19 }, */
/* Package(){0x00140005, 1, 0, 17 }, */
/* Package(){0x00140006, 1, 0, 17 }, */
})
Name(PR1, Package(){
/* Internal graphics - RS690 VGA, Bus1, Dev5 */
Package(){0x0005FFFF, 0, INTA, 0 },
Package(){0x0005FFFF, 1, INTB, 0 },
Package(){0x0005FFFF, 2, INTC, 0 },
Package(){0x0005FFFF, 3, INTD, 0 },
})
Name(APR1, Package(){
/* Internal graphics - RS690 VGA, Bus1, Dev5 */
Package(){0x0005FFFF, 0, 0, 18 },
Package(){0x0005FFFF, 1, 0, 19 },
/* Package(){0x0005FFFF, 2, 0, 20 }, */
/* Package(){0x0005FFFF, 3, 0, 17 }, */
})
Name(PS2, Package(){
/* The external GFX - Hooked to PCIe slot 2 */
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS2, Package(){
/* The external GFX - Hooked to PCIe slot 2 */
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
Name(PS4, Package(){
/* PCIe slot - Hooked to PCIe slot 4 */
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
Name(APS4, Package(){
/* PCIe slot - Hooked to PCIe slot 4 */
Package(){0x0000FFFF, 0, 0, 16 },
Package(){0x0000FFFF, 1, 0, 17 },
Package(){0x0000FFFF, 2, 0, 18 },
Package(){0x0000FFFF, 3, 0, 19 },
})
Name(PS5, Package(){
/* PCIe slot - Hooked to PCIe slot 5 */
Package(){0x0000FFFF, 0, INTB, 0 },
Package(){0x0000FFFF, 1, INTC, 0 },
Package(){0x0000FFFF, 2, INTD, 0 },
Package(){0x0000FFFF, 3, INTA, 0 },
})
Name(APS5, Package(){
/* PCIe slot - Hooked to PCIe slot 5 */
Package(){0x0000FFFF, 0, 0, 17 },
Package(){0x0000FFFF, 1, 0, 18 },
Package(){0x0000FFFF, 2, 0, 19 },
Package(){0x0000FFFF, 3, 0, 16 },
})
Name(PS6, Package(){
/* PCIe slot - Hooked to PCIe slot 6 */
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS6, Package(){
/* PCIe slot - Hooked to PCIe slot 6 */
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
Name(PS7, Package(){
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APS7, Package(){
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
Package(){0x0000FFFF, 0, 0, 19 },
Package(){0x0000FFFF, 1, 0, 16 },
Package(){0x0000FFFF, 2, 0, 17 },
Package(){0x0000FFFF, 3, 0, 18 },
})
Name(PCIB, Package(){
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
Package(){0x0005FFFF, 0, 0, 0x14 },
Package(){0x0005FFFF, 1, 0, 0x15 },
Package(){0x0005FFFF, 2, 0, 0x16 },
Package(){0x0005FFFF, 3, 0, 0x17 },
Package(){0x0006FFFF, 0, 0, 0x15 },
Package(){0x0006FFFF, 1, 0, 0x16 },
Package(){0x0006FFFF, 2, 0, 0x17 },
Package(){0x0006FFFF, 3, 0, 0x14 },
Package(){0x0007FFFF, 0, 0, 0x16 },
Package(){0x0007FFFF, 1, 0, 0x17 },
Package(){0x0007FFFF, 2, 0, 0x14 },
Package(){0x0007FFFF, 3, 0, 0x15 },
})
}

149
src/mainboard/amd/pistachio/acpi/sata.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* simple name description */
/*
Scope (_SB) {
Device(PCI0) {
Device(SATA) {
Name(_ADR, 0x00120000)
Include ("sata.asl")
}
}
}
*/
Name(STTM, Buffer(20) {
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
0x1f, 0x00, 0x00, 0x00
})
/* Start by clearing the PhyRdyChg bits */
Method(_INI) {
\_GPE._L1F()
}
Device(PMRY)
{
Name(_ADR, 0)
Method(_GTM, 0x0, NotSerialized) {
Return(STTM)
}
Method(_STM, 0x3, NotSerialized) {}
Device(PMST) {
Name(_ADR, 0)
Method(_STA,0) {
if (LGreater(P0IS,0)) {
return (0x0F) /* sata is visible */
}
else {
return (0x00) /* sata is missing */
}
}
}/* end of PMST */
Device(PSLA)
{
Name(_ADR, 1)
Method(_STA,0) {
if (LGreater(P1IS,0)) {
return (0x0F) /* sata is visible */
}
else {
return (0x00) /* sata is missing */
}
}
} /* end of PSLA */
} /* end of PMRY */
Device(SEDY)
{
Name(_ADR, 1) /* IDE Scondary Channel */
Method(_GTM, 0x0, NotSerialized) {
Return(STTM)
}
Method(_STM, 0x3, NotSerialized) {}
Device(SMST)
{
Name(_ADR, 0)
Method(_STA,0) {
if (LGreater(P2IS,0)) {
return (0x0F) /* sata is visible */
}
else {
return (0x00) /* sata is missing */
}
}
} /* end of SMST */
Device(SSLA)
{
Name(_ADR, 1)
Method(_STA,0) {
if (LGreater(P3IS,0)) {
return (0x0F) /* sata is visible */
}
else {
return (0x00) /* sata is missing */
}
}
} /* end of SSLA */
} /* end of SEDY */
/* SATA Hot Plug Support */
Scope(\_GPE) {
Method(_L1F,0x0,NotSerialized) {
if (\_SB.P0PR) {
if (LGreater(\_SB.P0IS,0)) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
store(one, \_SB.P0PR)
}
if (\_SB.P1PR) {
if (LGreater(\_SB.P1IS,0)) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
store(one, \_SB.P1PR)
}
if (\_SB.P2PR) {
if (LGreater(\_SB.P2IS,0)) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
store(one, \_SB.P2PR)
}
if (\_SB.P3PR) {
if (LGreater(\_SB.P3IS,0)) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
store(one, \_SB.P3PR)
}
}
}

93
src/mainboard/amd/pistachio/acpi/statdef.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Status and notification definitions */
#define STA_MISSING 0x00
#define STA_PRESENT 0x01
#define STA_ENABLED 0x03
#define STA_DISABLED 0x09
#define STA_INVISIBLE 0x0B
#define STA_UNAVAILABLE 0x0D
#define STA_VISIBLE 0x0F
/* SMBus status codes */
#define SMB_OK 0x00
#define SMB_UnknownFail 0x07
#define SMB_DevAddrNAK 0x10
#define SMB_DeviceError 0x11
#define SMB_DevCmdDenied 0x12
#define SMB_UnknownErr 0x13
#define SMB_DevAccDenied 0x17
#define SMB_Timeout 0x18
#define SMB_HstUnsuppProtocol 0x19
#define SMB_Busy 0x1A
#define SMB_PktChkError 0x1F
/* Device Object Notification Values */
#define NOTIFY_BUS_CHECK 0x00
#define NOTIFY_DEVICE_CHECK 0x01
#define NOTIFY_DEVICE_WAKE 0x02
#define NOTIFY_EJECT_REQUEST 0x03
#define NOTIFY_DEVICE_CHECK_JR 0x04
#define NOTIFY_FREQUENCY_ERROR 0x05
#define NOTIFY_BUS_MODE 0x06
#define NOTIFY_POWER_FAULT 0x07
#define NOTIFY_CAPABILITIES 0x08
#define NOTIFY_PLD_CHECK 0x09
#define NOTIFY_SLIT_UPDATE 0x0B
/* Battery Device Notification Values */
#define NOTIFY_BAT_STATUSCHG 0x80
#define NOTIFY_BAT_INFOCHG 0x81
#define NOTIFY_BAT_MAINTDATA 0x82
/* Power Source Object Notification Values */
#define NOTIFY_PWR_STATUSCHG 0x80
/* Thermal Zone Object Notification Values */
#define NOTIFY_TZ_STATUSCHG 0x80
#define NOTIFY_TZ_TRIPPTCHG 0x81
#define NOTIFY_TZ_DEVLISTCHG 0x82
#define NOTIFY_TZ_RELTBLCHG 0x83
/* Power Button Notification Values */
#define NOTIFY_POWER_BUTTON 0x80
/* Sleep Button Notification Values */
#define NOTIFY_SLEEP_BUTTON 0x80
/* Lid Notification Values */
#define NOTIFY_LID_STATUSCHG 0x80
/* Processor Device Notification Values */
#define NOTIFY_CPU_PPCCHG 0x80
#define NOTIFY_CPU_CSTATECHG 0x81
#define NOTIFY_CPU_THROTLCHG 0x82
/* User Presence Device Notification Values */
#define NOTIFY_USR_PRESNCECHG 0x80
/* Battery Device Notification Values */
#define NOTIFY_ALS_ILLUMCHG 0x80
#define NOTIFY_ALS_COLORTMPCHG 0x81
#define NOTIFY_ALS_RESPCHG 0x82

163
src/mainboard/amd/pistachio/acpi/usb.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* simple name description */
/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
Include ("usb.asl")
}
*/
Method(UCOC, 0) {
Sleep(20)
Store(0x13,CMTI)
Store(0,GPSL)
}
/* USB Port 0 overcurrent uses Gpm 0 */
If(LLessEqual(UOM0,9)) {
Scope (\_GPE) {
Method (_L13) {
UCOC()
if(LEqual(GPB0,PLC0)) {
Not(PLC0,PLC0)
Store(PLC0, \_SB.PT0D)
}
}
}
}
/* USB Port 1 overcurrent uses Gpm 1 */
If (LLessEqual(UOM1,9)) {
Scope (\_GPE) {
Method (_L14) {
UCOC()
if (LEqual(GPB1,PLC1)) {
Not(PLC1,PLC1)
Store(PLC1, \_SB.PT1D)
}
}
}
}
/* USB Port 2 overcurrent uses Gpm 2 */
If (LLessEqual(UOM2,9)) {
Scope (\_GPE) {
Method (_L15) {
UCOC()
if (LEqual(GPB2,PLC2)) {
Not(PLC2,PLC2)
Store(PLC2, \_SB.PT2D)
}
}
}
}
/* USB Port 3 overcurrent uses Gpm 3 */
If (LLessEqual(UOM3,9)) {
Scope (\_GPE) {
Method (_L16) {
UCOC()
if (LEqual(GPB3,PLC3)) {
Not(PLC3,PLC3)
Store(PLC3, \_SB.PT3D)
}
}
}
}
/* USB Port 4 overcurrent uses Gpm 4 */
If (LLessEqual(UOM4,9)) {
Scope (\_GPE) {
Method (_L19) {
UCOC()
if (LEqual(GPB4,PLC4)) {
Not(PLC4,PLC4)
Store(PLC4, \_SB.PT4D)
}
}
}
}
/* USB Port 5 overcurrent uses Gpm 5 */
/*
* If (LLessEqual(UOM5,9)) {
* Scope (\_GPE) {
* Method (_L1A) {
* UCOC()
* if (LEqual(GPB5,PLC5)) {
* Not(PLC5,PLC5)
* Store(PLC5, \_SB.PT5D)
* }
* }
* }
* }
*/
/* USB Port 6 overcurrent uses Gpm 6 */
If (LLessEqual(UOM6,9)) {
Scope (\_GPE) {
/* Method (_L1C) { */
Method (_L06) {
UCOC()
if (LEqual(GPB6,PLC6)) {
Not(PLC6,PLC6)
Store(PLC6, \_SB.PT6D)
}
}
}
}
/* USB Port 7 overcurrent uses Gpm 7 */
If (LLessEqual(UOM7,9)) {
Scope (\_GPE) {
/* Method (_L1D) { */
Method (_L07) {
UCOC()
if (LEqual(GPB7,PLC7)) {
Not(PLC7,PLC7)
Store(PLC7, \_SB.PT7D)
}
}
}
}
/* USB Port 8 overcurrent uses Gpm 8 */
If (LLessEqual(UOM8,9)) {
Scope (\_GPE) {
Method (_L17) {
if (LEqual(G8IS,PLC8)) {
Not(PLC8,PLC8)
Store(PLC8, \_SB.PT8D)
}
}
}
}
/* USB Port 9 overcurrent uses Gpm 9 */
If (LLessEqual(UOM9,9)) {
Scope (\_GPE) {
Method (_L0E) {
if (LEqual(G9IS,0)) {
Store(1,\_SB.PT9D)
}
}
}
}

755
src/mainboard/amd/pistachio/acpi_tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
#include <arch/cpu.h>
#define DUMP_ACPI_TABLES 0
/*
* Assume the max pstate number is 8
* 0x21(33 bytes) is one package length of _PSS package
*/
#define Maxpstate 8
#define Defpkglength 0x21
#if DUMP_ACPI_TABLES == 1
static void dump_mem(u32 start, u32 end)
{
u32 i;
print_debug("dump_mem:");
for (i = start; i < end; i++) {
if ((i & 0xf) == 0) {
printk_debug("\n%08x:", i);
}
printk_debug(" %02x", (u8)*((u8 *)i));
}
print_debug("\n");
}
#endif
extern u8 AmlCode[];
extern u8 AmlCode_ssdt[];
#if ACPI_SSDTX_NUM >= 1
extern u8 AmlCode_ssdt2[];
extern u8 AmlCode_ssdt3[];
extern u8 AmlCode_ssdt4[];
extern u8 AmlCode_ssdt5[];
#endif
#define IO_APIC_ADDR 0xfec00000UL
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
return current;
}
unsigned long acpi_fill_madt(unsigned long current)
{
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write SB600 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edige-triggered, Active high */
/* create all subtables for processors */
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
/* 1: LINT1 connect to NMI */
return current;
}
extern void get_bus_conf(void);
extern void update_ssdt(void *ssdt);
void update_ssdtx(void *ssdtx, int i)
{
uint8_t *PCI;
uint8_t *HCIN;
uint8_t *UID;
PCI = ssdtx + 0x32;
HCIN = ssdtx + 0x39;
UID = ssdtx + 0x40;
if (i < 7) {
*PCI = (uint8_t) ('4' + i - 1);
} else {
*PCI = (uint8_t) ('A' + i - 1 - 6);
}
*HCIN = (uint8_t) i;
*UID = (uint8_t) (i + 3);
/* FIXME: need to update the GSI id in the ssdtx too */
}
/*
* Details about this algorithm , refert to BDKG 10.5.1
* Two parts are included, the another is the DSDT reconstruction process
*/
u32 pstates_algorithm(acpi_header_t * dsdt)
{
u8 processor_brand[49];
u32 *v;
struct cpuid_result cpuid1;
typedef struct power_limit_encoding {
u8 socket_type;
u8 cmp_cap;
u8 pwr_lmt;
u32 power_limit;
};
u8 Max_fid, Max_vid, Start_fid, Start_vid, Min_fid, Min_vid;
u16 Max_feq;
u8 Pstate_fid[10];
u16 Pstate_feq[10];
u8 Pstate_vid[10];
u32 Pstate_power[10];
u32 Pstate_volt[10];
u8 PstateStep, PstateStep_coef;
u8 IntPstateSup;
u8 Pstate_num;
u16 Cur_feq;
u8 Cur_fid;
u8 cmp_cap, pwr_lmt;
u32 power_limit = 0;
u8 index;
u32 i, j;
u32 processor_length, scope_length;
msr_t msr;
u8 *dsdt_pointer;
u8 *pointer1;
u8 *pointer2;
u8 byte_index;
u32 old_dsdt_length, new_dsdt_length;
u32 corefeq, power, transitionlatency, busmasterlatency, control,
status;
u32 new_package_length;
u8 sum, checksum;
u32 fid_multiplier;
static struct power_limit_encoding TDP[20] = {
{0x11, 0x0, 0x8, 62},
{0x11, 0x1, 0x8, 89},
{0x11, 0x1, 0xa, 103},
{0x11, 0x1, 0xc, 125},
{0x11, 0x0, 0x2, 15},
{0x11, 0x0, 0x4, 35},
{0x11, 0x1, 0x2, 35},
{0x11, 0x0, 0x5, 45},
{0x11, 0x1, 0x7, 76},
{0x11, 0x1, 0x6, 65},
{0x11, 0x1, 0x8, 89},
{0x11, 0x0, 0x1, 8},
{0x11, 0x1, 0x1, 22},
{0x12, 0x0, 0x6, 25},
{0x12, 0x0, 0x1, 8},
{0x12, 0x0, 0x2, 9},
{0x12, 0x0, 0x4, 15},
{0x12, 0x0, 0xc, 35},
{0x12, 0x1, 0xc, 35},
{0x12, 0x1, 0x4, 20}
};
/* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
cpuid1 = cpuid(0x80000002);
v = (u32 *) processor_brand;
v[0] = cpuid1.eax;
v[1] = cpuid1.ebx;
v[2] = cpuid1.ecx;
v[3] = cpuid1.edx;
cpuid1 = cpuid(0x80000003);
v[4] = cpuid1.eax;
v[5] = cpuid1.ebx;
v[6] = cpuid1.ecx;
v[7] = cpuid1.edx;
cpuid1 = cpuid(0x80000004);
v[8] = cpuid1.eax;
v[9] = cpuid1.ebx;
v[10] = cpuid1.ecx;
v[11] = cpuid1.edx;
processor_brand[48] = 0;
printk_info("processor_brand=%s\n", processor_brand);
/*
* Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
* socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
* cmp_cap : 0x0 SingleCore ; 0x1 DualCore
*/
printk_info("Pstates Algorithm ...\n");
cmp_cap =
(pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
0x3000) >> 12;
cpuid1 = cpuid(0x80000001);
pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14);
for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++)
if (TDP[index].socket_type == CPU_SOCKET_TYPE &&
TDP[index].cmp_cap == cmp_cap &&
TDP[index].pwr_lmt == pwr_lmt) {
power_limit = TDP[index].power_limit;
}
/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
cpuid1 = cpuid(0x80000007);
if ((cpuid1.edx & 0x6) != 0x6) {
printk_info("No valid set of P-states\n");
return 0;
}
msr = rdmsr(0xc0010042);
Max_fid = (msr.lo & 0x3F0000) >> 16;
Start_fid = (msr.lo & 0x3F00) >> 8;
Max_vid = (msr.hi & 0x3F0000) >> 16;
Start_vid = (msr.hi & 0x3F00) >> 8;
PstateStep = (msr.hi & 0x1000000) >> 24;
IntPstateSup = (msr.hi & 0x20000000) >> 29;
/*
* The P1...P[Min+1] VID need PstateStep to calculate
* P[N] = P[N-1]VID + 2^PstateStep
* PstateStep_coef = 2^PstateStep
*/
if (PstateStep == 0)
PstateStep_coef = 1;
else
PstateStep_coef = 2;
if (IntPstateSup == 0) {
printk_info("No intermediate P-states are supported\n");
return 0;
}
/*get the multipier of the fid frequency */
/*
* In RevG, 100MHz step is added
*/
cpuid1 = cpuid(0x80000007);
fid_multiplier = ((cpuid1.edx & 0x40) >> 6) * 100;
/*
* Formula1: CPUFreq = FID * fid_multiplier + 800
* Formula2: CPUVolt = 1550 - VID * 25 (mv)
* Formula3: Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2))
*/
/* Construct P0(P[Max]) state */
Pstate_num = 0;
Max_feq = Max_fid * fid_multiplier + 800;
if (Max_fid == 0x2A && Max_vid != 0x0) {
Min_fid = 0x2;
Pstate_fid[0] = Start_fid + 0xA; /* Start Frequency + 1GHz */
Pstate_feq[0] = Pstate_fid[0] * fid_multiplier + 800;
Min_vid = Start_vid;
Pstate_vid[0] = Max_vid + 0x2; /* Maximum Voltage - 50mV */
Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
Pstate_power[0] = power_limit * 1000; /* mw */
Pstate_num++;
} else {
Min_fid = Start_fid;
Pstate_fid[0] = Max_fid;
Pstate_feq[0] = Max_feq;
Min_vid = Start_vid;
Pstate_vid[0] = Max_vid + 0x2;
Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
Pstate_power[0] = power_limit * 1000; /* mw */
Pstate_num++;
}
Cur_feq = Max_feq;
Cur_fid = Max_fid;
/* Construct P1 state */
if (((Max_fid & 0x1) != 0) && ((Max_fid - 0x1) >= (Min_fid + 0x8))) { /* odd value */
Pstate_fid[1] = Max_fid - 0x1;
Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
Cur_fid = Pstate_fid[1];
Cur_feq = Pstate_feq[1];
if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* odd value */
Pstate_vid[1] = Pstate_vid[0] + 0x1;
Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
Pstate_power[1] =
(unsigned long long)Pstate_power[0] *
Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
}
if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* even value */
Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
Pstate_power[1] =
(unsigned long long)Pstate_power[0] *
Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
}
Pstate_num++;
}
if (((Max_fid & 0x1) == 0) && ((Max_fid - 0x2) >= (Min_fid + 0x8))) { /* even value */
Pstate_fid[1] = Max_fid - 0x2;
Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
Cur_fid = Pstate_fid[1];
Cur_feq = Pstate_feq[1];
if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* odd value */
Pstate_vid[1] = Pstate_vid[0] + 0x1;
Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
Pstate_power[1] =
(unsigned long long)Pstate_power[0] *
Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
}
if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* even value */
Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
Pstate_power[1] =
(unsigned long long)Pstate_power[0] *
Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
}
Pstate_num++;
}
/* Construct P2...P[Min-1] state */
Cur_fid = Cur_fid - 0x2;
Cur_feq = Cur_fid * fid_multiplier + 800;
while (Cur_feq >= ((Min_fid * fid_multiplier) + 800) * 2) {
Pstate_fid[Pstate_num] = Cur_fid;
Pstate_feq[Pstate_num] =
Pstate_fid[Pstate_num] * fid_multiplier + 800;
Cur_fid = Cur_fid - 0x2;
Cur_feq = Cur_fid * fid_multiplier + 800;
if (Pstate_vid[Pstate_num - 1] >= Min_vid) {
Pstate_vid[Pstate_num] = Pstate_vid[Pstate_num - 1];
Pstate_volt[Pstate_num] = Pstate_volt[Pstate_num - 1];
Pstate_power[Pstate_num] = Pstate_power[Pstate_num - 1];
} else {
Pstate_vid[Pstate_num] =
Pstate_vid[Pstate_num - 1] + PstateStep_coef;
Pstate_volt[Pstate_num] =
1550 - Pstate_vid[Pstate_num] * 25;
Pstate_power[Pstate_num] =
(unsigned long long)Pstate_power[0] *
Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
Pstate_volt[Pstate_num] / (Pstate_feq[0] *
Pstate_volt[0] *
Pstate_volt[0]);
}
Pstate_num++;
}
/* Constuct P[Min] State */
if (Max_fid == 0x2A && Max_vid != 0x0) {
Pstate_fid[Pstate_num] = 0x2;
Pstate_feq[Pstate_num] =
Pstate_fid[Pstate_num] * fid_multiplier + 800;
Pstate_vid[Pstate_num] = Min_vid;
Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
Pstate_power[Pstate_num] =
(unsigned long long)Pstate_power[0] *
Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
Pstate_volt[0]);
Pstate_num++;
} else {
Pstate_fid[Pstate_num] = Start_fid;
Pstate_feq[Pstate_num] =
Pstate_fid[Pstate_num] * fid_multiplier + 800;
Pstate_vid[Pstate_num] = Min_vid;
Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
Pstate_power[Pstate_num] =
(unsigned long long)Pstate_power[0] *
Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
Pstate_volt[0]);
Pstate_num++;
}
/* Print Pstate feq,vid,volt,power */
for (index = 0; index < Pstate_num; index++) {
printk_info("Pstate_feq[%d] = %dMHz\t", index,
Pstate_feq[index]);
printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
printk_info("Pstate_volt[%d] = %dmv\t", index,
Pstate_volt[index]);
printk_info("Pstate_power[%d] = %dmw\n", index,
Pstate_power[index]);
}
/*
* Modify the DSDT Table to put the actural _PSS package
* corefeq-->Pstate_feq[index] power-->Pstate_power[index] transitionlatency-->0x64 busmasterlatency-->0x7,
* control-->0xE8202C00| Pstate_vid[index]<<6 | Pstate_fid[index]
* status --> Pstate_vid[index]<<6 | Pstate_fid[index]
* Get the _PSS control method Sig.
*/
dsdt_pointer = (u8 *) dsdt;
old_dsdt_length = dsdt->length;
new_dsdt_length = old_dsdt_length;
printk_info("DSDT reconstruction...\n");
for (i = 0x20; i < new_dsdt_length; i++)
if ((*(dsdt_pointer + i) == '_')
&& (*(dsdt_pointer + i + 1) == 'P')
&& (*(dsdt_pointer + i + 2) == 'S')
&& (*(dsdt_pointer + i + 3) == 'S')) {
if ((*(dsdt_pointer + i + 4) !=
0x12) | (*(dsdt_pointer + i + 5) !=
0x4B) | (*(dsdt_pointer + i + 6) !=
0x10)) {
printk_info
("Error:No _PSS package leader byte!\n");
} else {
new_package_length =
0x10B - Defpkglength * (Maxpstate -
Pstate_num);
/* two Pstates length will larger than 63, so we need not worry about the length */
if (new_package_length > 63) {
*(dsdt_pointer + i + 5) =
0x40 | (new_package_length & 0xf);
*(dsdt_pointer + i + 6) =
(new_package_length & 0xff0) >> 4;
}
*(dsdt_pointer + i + 7) = Pstate_num;
}
if ((*(dsdt_pointer + i + 8) !=
0x12) | (*(dsdt_pointer + i + 9) !=
0x20) | (*(dsdt_pointer + i + 10) != 0x6))
printk_info
("Error:No package leader for the first Pstate!\n");
for (index = 0; index < Pstate_num; index++) {
corefeq = Pstate_feq[index];
power = Pstate_power[index];
transitionlatency = 0x64;
busmasterlatency = 0x7;
control =
0xE8202C00 | (Pstate_vid[index] << 6) |
Pstate_fid[index];
status =
(Pstate_vid[index] << 6) |
Pstate_fid[index];
for (byte_index = 0; byte_index < 4;
byte_index++) {
*(dsdt_pointer + i + 0xC +
Defpkglength * index + byte_index) =
corefeq >> (8 * byte_index);
*(dsdt_pointer + i + 0xC +
Defpkglength * index + 0x5 +
byte_index) =
power >> (8 * byte_index);
*(dsdt_pointer + i + 0xC +
Defpkglength * index + 0x5 * 2 +
byte_index) =
transitionlatency >> (8 * byte_index);
*(dsdt_pointer + i + 0xC +
Defpkglength * index + 0x5 * 3 +
byte_index) =
busmasterlatency >> (8 * byte_index);
*(dsdt_pointer + i + 0xC +
Defpkglength * index + 0x5 * 4 +
byte_index) =
control >> (8 * byte_index);
*(dsdt_pointer + i + 0xC +
Defpkglength * index + 0x5 * 5 +
byte_index) =
status >> (8 * byte_index);
}
}
pointer1 =
dsdt_pointer + i + 8 + Pstate_num * Defpkglength;
pointer2 =
dsdt_pointer + i + 8 + Maxpstate * Defpkglength;
while (pointer2 < dsdt_pointer + new_dsdt_length) {
*pointer1 = *pointer2;
pointer1++;
pointer2++;
}
/* Recalcute the DSDT length */
new_dsdt_length =
new_dsdt_length - Defpkglength * (Maxpstate -
Pstate_num);
/* Search the first processor(CPUx) item and recalculate the processor length */
for (j = 0; (dsdt_pointer + i - j) > dsdt_pointer; j++) {
if ((*(dsdt_pointer + i - j) == 'C')
&& (*(dsdt_pointer + i - j + 1) == 'P')
&& (*(dsdt_pointer + i - j + 2) == 'U')) {
processor_length =
((*(dsdt_pointer + i - j - 1) << 4)
| (*(dsdt_pointer + i - j - 2) &
0xf));
processor_length =
processor_length -
Defpkglength * (Maxpstate -
Pstate_num);
*(dsdt_pointer + i - j - 2) =
(processor_length & 0xf) | 0x40;
*(dsdt_pointer + i - j - 1) =
(processor_length & 0xff0) >> 4;
break;
}
}
/* Search the first scope(_PR_) item and recalculate the scope length */
for (j = 0; (dsdt_pointer + i - j) > dsdt_pointer; j++) {
if ((*(dsdt_pointer + i - j) == '_')
&& (*(dsdt_pointer + i - j + 1) == 'P')
&& (*(dsdt_pointer + i - j + 2) == 'R')
&& (*(dsdt_pointer + i - j + 3) == '_')) {
scope_length =
((*(dsdt_pointer + i - j - 1) << 4)
| (*(dsdt_pointer + i - j - 2) &
0xf));
scope_length =
scope_length -
Defpkglength * (Maxpstate -
Pstate_num);
*(dsdt_pointer + i - j - 2) =
(scope_length & 0xf) | 0x40;
*(dsdt_pointer + i - j - 1) =
(scope_length & 0xff0) >> 4;
break;
}
}
}
/* Recalculate the DSDT length and fill back to the table */
*(dsdt_pointer + 0x4) = new_dsdt_length;
*(dsdt_pointer + 0x5) = new_dsdt_length >> 8;
/*
* Recalculate the DSDT checksum and fill back to the table
* We must make sure the sum of the whole table is 0
*/
sum = 0;
for (i = 0; i < new_dsdt_length; i++)
if (i != 9)
sum = sum + *(dsdt_pointer + i);
checksum = 0x100 - sum;
*(dsdt_pointer + 0x9) = checksum;
/*Check the DSDT Table */
/*
* printk_info("The new DSDT table length is %x\n", new_dsdt_length);
* printk_info("Details is as below:\n");
* for(i=0; i< new_dsdt_length; i++){
* printk_info("%x\t",(unsigned char)*(dsdt_pointer+i));
* if( ((i+1)&0x7) == 0x0)
* printk_info("**0x%x**\n",i-7);
*}
*/
return 1;
}
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16byte */
start = (start + 0x0f) & -0x10;
current = start;
printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt);
acpi_write_rsdt(rsdt);
/*
* We explicitly add these tables later on:
*/
/* If we want to use HPET Timers Linux wants an MADT */
printk_debug("ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdt, hpet);
printk_debug("ACPI: * MADT\n");
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
acpi_add_table(rsdt, madt);
#if 0
/* SRAT */
printk_debug("ACPI: * SRAT\n");
srat = (acpi_srat_t *) current;
acpi_create_srat(srat);
current += srat->header.length;
acpi_add_table(rsdt, srat);
/* SLIT */
printk_debug("ACPI: * SLIT\n");
slit = (acpi_slit_t *) current;
acpi_create_slit(slit);
current += slit->header.length;
acpi_add_table(rsdt, slit);
#endif
/* SSDT */
printk_debug("ACPI: * SSDT\n");
ssdt = (acpi_header_t *) current;
current += ((acpi_header_t *) AmlCode_ssdt)->length;
memcpy((void *)ssdt, (void *)AmlCode_ssdt,
((acpi_header_t *) AmlCode_ssdt)->length);
/* Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c */
update_ssdt((void *)ssdt);
/* recalculate checksum */
ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((u8 *)ssdt, ssdt->length);
acpi_add_table(rsdt, ssdt);
#if ACPI_SSDTX_NUM >= 1
/* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
if ((sysconf.pci1234[i] & 1) != 1)
continue;
uint8_t c;
if (i < 7) {
c = (uint8_t) ('4' + i - 1);
} else {
c = (uint8_t) ('A' + i - 1 - 6);
}
printk_debug("ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */
current = (current + 0x07) & -0x08;
ssdtx = (acpi_header_t *) current;
switch (sysconf.hcid[i]) {
case 1: /* 8132 */
p = AmlCode_ssdt2;
break;
case 2: /* 8151 */
p = AmlCode_ssdt3;
break;
case 3: /* 8131 */
p = AmlCode_ssdt4;
break;
default:
/* HTX no io apic */
p = AmlCode_ssdt5;
break;
}
current += ((acpi_header_t *) p)->length;
memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *) p)->length);
update_ssdtx((void *)ssdtx, i);
ssdtx->checksum = 0;
ssdtx->checksum =
acpi_checksum((u8 *)ssdtx, ssdtx->length);
acpi_add_table(rsdt, ssdtx);
}
#endif
/* FACS */
printk_debug("ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
/* DSDT */
printk_debug("ACPI: * DSDT\n");
dsdt = (acpi_header_t *) current;
memcpy((void *)dsdt, (void *)AmlCode,
((acpi_header_t *) AmlCode)->length);
if (!pstates_algorithm(dsdt))
printk_debug("pstates_algorithm error!\n");
else
printk_debug("pstates_algorithm success.\n");
current += dsdt->length;
printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length);
/* FDAT */
printk_debug("ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdt, fadt);
#if DUMP_ACPI_TABLES == 1
printk_debug("rsdp\n");
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
printk_debug("rsdt\n");
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
printk_debug("madt\n");
dump_mem(madt, ((void *)madt) + madt->header.length);
printk_debug("srat\n");
dump_mem(srat, ((void *)srat) + srat->header.length);
printk_debug("slit\n");
dump_mem(slit, ((void *)slit) + slit->header.length);
printk_debug("ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
printk_debug("fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length);
#endif
printk_info("ACPI: done.\n");
return current;
}

242
src/mainboard/amd/pistachio/cache_as_ram_auto.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#define __ROMCC__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#define DIMM0 0x50
#define DIMM1 0x51
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#define post_code(x) outb(x, 0x80)
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
/* called in raminit_f.c */
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#if USE_FALLBACK_IMAGE == 1
#include "northbridge/amd/amdk8/early_ht.c"
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Is this a cpu only reset? Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal()) { /* RTC already inited */
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sb600_lpc_port80();
/* sb600_pci_port80(); */
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
} else {
goto fallback_image;
}
normal_image:
post_code(0x01);
__asm__ volatile ("jmp __normal_image": /* outputs */
:"a" (bist), "b"(cpu_init_detectedx)); /* inputs */
fallback_image:
post_code(0x02);
}
#endif /* USE_FALLBACK_IMAGE == 1 */
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
u32 bsp_apicid = 0;
msr_t msr;
struct sys_info *sysinfo =
(struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE -
DCACHE_RAM_GLOBAL_VAR_SIZE);
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
enable_rs690_dev8();
sb600_lpc_init();
/* Pistachio used a FPGA to enable serial debug instead of a SIO
* and it doens't require any special setup. */
uart_init();
console_init();
post_code(0x03);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
setup_pistachio_resource_map();
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();
#endif
wait_all_aps_started(bsp_apicid);
/* it will set up chains and store link pair for optimization later,
* it will init sblnk and sbbusn, nodes, sbdn */
ht_setup_chains_x(sysinfo);
/* run _early_setup before soft-reset. */
rs690_early_setup();
sb600_early_setup();
post_code(0x04);
msr = rdmsr(0xc0010042);
printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
msr = rdmsr(0xc0010042);
printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
post_code(0x05);
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
printk_debug("needs_reset=0x%x\n", needs_reset);
post_code(0x06);
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now; */
printk_debug("sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n",
sysinfo->nodes, sysinfo->ctrl, spd_addr);
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
post_code(0x07);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_code(0x08);
rs690_before_pci_init();
sb600_before_pci_init();
post_cache_as_ram();
}

26
src/mainboard/amd/pistachio/chip.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern struct chip_operations mainboard_amd_pistachio_ops;
struct mainboard_amd_pistachio_config
{
unsigned long uma_size; /* How many UMA should be used in memory for TOP. */
};

119
src/mainboard/amd/pistachio/cmos.layout Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
##
##
entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
#96 288 r 0 temporary_filler
0 384 r 0 reserved_memory
384 1 e 4 boot_option
385 1 e 4 last_boot
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 dual_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
420 4 e 7 boot_second
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Network
7 1 HDD
7 2 Floppy
7 8 Fallback_Network
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 DDR400
8 1 DDR333
8 2 DDR266
8 3 DDR200
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 983 984

199
src/mainboard/amd/pistachio/fadt.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* ACPI - create the Fixed ACPI Description Tables (FADT)
*/
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
/*extern*/ u16 pm_base = 0x800;
/* pm_base should be set in sb acpi */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
pm_base &= 0xFFFF;
printk_debug("pm_base: 0x%04x\n", pm_base);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = 244;
header->revision = 1;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, "COREBOOT", 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = 0;
fadt->firmware_ctrl = (u32) facs;
fadt->dsdt = (u32) dsdt;
/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9;
/* disable system management mode by setting to 0: */
fadt->smi_cmd = 0;
fadt->acpi_enable = 0xf0;
fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
/* CpuControl is in \_PR.CPU0, 6 bytes */
pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
* the contents of the PM registers at
* index 20-2B to decode ACPI I/O address.
* AcpiSmiEn & SmiCmdEn*/
pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
fadt->pm1b_evt_blk = 0x0000;
fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
fadt->pm1b_cnt_blk = 0x0000;
fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
fadt->gpe0_blk = ACPI_GPE0_BLK;
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 8;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0xe3;
fadt->p_lvl2_lat = 101;
fadt->p_lvl3_lat = 1001;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->day_alrm = 0; /* 0x7d these have to be */
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
fadt->century = 0; /* 0x7f to make rtc alrm work */
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
fadt->flags = 0x0001c1a5;/* 0x25; */
fadt->res2 = 0;
fadt->reset_reg.space_id = 1;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 6;
fadt->x_firmware_ctl_l = (u32) facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32) dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 4;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 2;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = 0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
}

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src/mainboard/amd/pistachio/get_bus_conf.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS==1
#include <cpu/amd/dualcore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_isa;
u8 bus_rs690[8];
u8 bus_sb600[2];
u32 apicid_sb600;
/*
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
* You may need to preset pci1234 for HTIO board,
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
*/
u32 pci1234x[] = {
0x0000ff0,
};
/*
* HT Chain device num, actually it is unit id base of every ht device in chain,
* assume every chain only have 4 ht device at most
*/
u32 hcdnx[] = {
0x20202020,
};
u32 bus_type[256];
u32 sbdn_rs690;
u32 sbdn_sb600;
extern void get_sblk_pci1234(void);
static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
device_t dev;
int i, j;
if (get_bus_conf_done == 1)
return; /* do it only once */
get_bus_conf_done = 1;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for (i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
get_sblk_pci1234();
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
sbdn_rs690 = sysconf.sbdn;
sbdn_sb600 = 0;
for (i = 0; i < 2; i++) {
bus_sb600[i] = 0;
}
for (i = 0; i < 8; i++) {
bus_rs690[i] = 0;
}
for (i = 0; i < 256; i++) {
bus_type[i] = 0; /* default ISA bus. */
}
bus_type[0] = 1; /* pci */
bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb600[0] = bus_rs690[0];
bus_type[bus_rs690[0]] = 1;
/* sb600 */
dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
if (dev) {
bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
for (j = bus_sb600[1]; j < bus_isa; j++)
bus_type[j] = 1;
}
/* rs690 */
for (i = 1; i < 8; i++) {
dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
if (dev) {
bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
if(255 != bus_rs690[i]) {
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
bus_type[bus_rs690[i]] = 1; /* PCI bus. */
}
}
}
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
apicid_sb600 = apicid_base + 0;
}

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src/mainboard/amd/pistachio/irq_tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/
#include <console/console.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#include <arch/pirq_routing.h>
#include <cpu/amd/amdk8_sysconf.h>
extern void get_bus_conf(void);
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
u8 slot, u8 rfu)
{
pirq_info->bus = bus;
pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0;
pirq_info->irq[1].link = link1;
pirq_info->irq[1].bitmap = bitmap1;
pirq_info->irq[2].link = link2;
pirq_info->irq[2].bitmap = bitmap2;
pirq_info->irq[3].link = link3;
pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
extern u32 sbdn_sb600;
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
struct irq_info *pirq_info;
u32 slot_num;
u8 *v;
u8 sum = 0;
int i;
get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
/* Align the table to be 16 byte aligned. */
addr += 15;
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk_info("Writing IRQ routing tables to 0x%x...", addr);
pirq = (void *)(addr);
v = (u8 *) (addr);
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb600[0];
pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4;
pirq->exclusive_irqs = 0;
pirq->rtr_vendor = 0x1002;
pirq->rtr_device = 0x4384;
pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu));
pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4,
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;
slot_num++;
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
sum += v[i];
sum = pirq->checksum - sum;
if (sum != pirq->checksum) {
pirq->checksum = sum;
}
printk_info("write_pirq_routing_table done.\n");
return (unsigned long)pirq_info;
}

333
src/mainboard/amd/pistachio/mainboard.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include "chip.h"
#define ADT7475_ADDRESS 0x2E
#define SMBUS_IO_BASE 0x1000
extern u8 pm_ioread(u8 reg);
extern void pm_iowrite(u8 reg, u8 value);
extern u8 pm2_ioread(u8 reg);
extern void pm2_iowrite(u8 reg, u8 value);
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
#define ADT7475_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address)
#define ADT7475_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address, val)
/********************************************************
* pistachio uses a BCM5787 as on-board NIC.
* It has a pin named LOW_POWER to enable it into LOW POWER state.
* In order to run NIC, we should let it out of Low power state. This pin is
* controlled by GPM8.
* RPR4.2.3 GPM as GPIO
* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
* I/O C50, C51, C52, PM I/O94, 95, 96.
* RPR4.2.3.1 GPM pins as Input
* RPR4.2.3.2 GPM pins as Output
* The R77 (on BRASS) / R81 (on Bronze) is not load!
* So NIC can work whether this function runs.
********************************************************/
static void enable_onboard_nic()
{
u8 byte;
printk_info("enable_onboard_nic.\n");
/* enable GPM8 output */
byte = pm_ioread(0x95);
byte &= 0xfe;
pm_iowrite(0x95, byte);
/* GPM8 outputs low. */
byte = pm_ioread(0x94);
byte &= 0xfe;
pm_iowrite(0x94, byte);
}
/*
* set thermal config
*/
static void set_thermal_config()
{
u8 byte, byte2;
u16 word;
u32 dword;
device_t sm_dev;
struct bus pbus;
/* set adt7475 */
ADT7475_write_byte(0x40, 0x04);
/* Config Register 6 */
ADT7475_write_byte(0x10, 0x00);
/* Config Register 7 */
ADT7475_write_byte(0x11, 0x00);
/* set Offset 64 format, enable THERM on Remote 1& Remote 2 */
ADT7475_write_byte(0x7c, 0xa0);
/* No offset for remote 2 */
ADT7475_write_byte(0x72, 0x00);
/* PWM 1 configuration register CPU fan controlled by CPU Thermal Diode */
ADT7475_write_byte(0x5c, 0x02);
/* PWM 3 configuration register Case fan controlled by 690 temp */
ADT7475_write_byte(0x5e, 0x42);
/* remote 1 low temp limit */
ADT7475_write_byte(0x4e, 0x00);
/* remote 1 High temp limit (90C) */
ADT7475_write_byte(0x4f, 0x9a);
/* remote2 Low Temp Limit */
ADT7475_write_byte(0x52, 0x00);
/* remote2 High Limit (90C) */
ADT7475_write_byte(0x53, 0x9a);
/* remote 1 therm temp limit (95C) */
ADT7475_write_byte(0x6a, 0x9f);
/* remote 2 therm temp limit (95C) */
ADT7475_write_byte(0x6c, 0x9f);
/* PWM 1 minimum duty cycle (37%) */
ADT7475_write_byte(0x64, 0x60);
/* PWM 1 Maximum duty cycle (100%) */
ADT7475_write_byte(0x38, 0xff);
/* PWM 3 minimum duty cycle (37%) */
ADT7475_write_byte(0x66, 0x60);
/* PWM 3 Maximum Duty Cycle (100%) */
ADT7475_write_byte(0x3a, 0xff);
/* Remote 1 temperature Tmin (32C) */
ADT7475_write_byte(0x67, 0x60);
/* Remote 2 temperature Tmin (32C) */
ADT7475_write_byte(0x69, 0x60);
/* remote 1 Trange (53C ramp range) */
ADT7475_write_byte(0x5f, 0xe8);
/* remote 2 Trange (53C ramp range) */
ADT7475_write_byte(0x61, 0xe8);
/* PWM2 Duty cycle */
ADT7475_write_byte(0x65, 0x00);
/* PWM2 Disabled */
ADT7475_write_byte(0x5d, 0x80);
/* PWM2 Max Duty Cycle */
ADT7475_write_byte(0x39, 0x00);
/* Config Register 3 - enable smbalert & therm */
ADT7475_write_byte(0x78, 0x03);
/* Config Register 4 - enable therm output */
ADT7475_write_byte(0x7d, 0x09);
/* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 2 fault, SmbAlert Fan for Therm Timer event */
ADT7475_write_byte(0x75, 0x2a);
/* Config Register 1 Set Start bit */
ADT7475_write_byte(0x40, 0x05);
/* Read status register to clear any old errors */
byte2 = ADT7475_read_byte(0x42);
byte = ADT7475_read_byte(0x41);
/* remote 1 temperature offset */
ADT7475_write_byte(0x70, 0x00);
printk_info("Init adt7475 end , status 0x42 %02x, status 0x41 %02x\n",
byte2, byte);
/* sb600 setting for thermal config. Set SB600 GPM5 to trigger ACPI event */
/* set GPM5 as GPM5, not DDR3_memory disable */
byte = pm_ioread(0x8f);
byte |= 1 << 6; /* enable GPE */
pm_iowrite(0x8f, byte);
/* GPM5 as GPIO not USB OC */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
dword =
pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x64);
dword |= 1 << 19;
pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x64, dword);
/* Enable Client Management Index/Data registers */
dword =
pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x78);
dword |= 1 << 11; /* Cms_enable */
pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x78, dword);
/* MiscfuncEnable */
byte =
pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x41);
byte |= (1 << 5);
pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x41, byte);
/* set GPM5 as input */
/* step1: set index register 0C50h to 13h (miscellaneous control) */
outb(0x13, 0xC50); /* CMIndex */
/* step2: set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
byte = inb(0xC51); /* CMData */
byte &= 0x3f;
byte |= 1 << 6;
outb(byte, 0xC51);
/* step3: set GPM port 0C52h appropriate bits to 1 to tri-state the GPM port */
byte = inb(0xc52); /* GpmPort */
byte |= 1 << 5;
outb(byte, 0xc52);
/* step4: set CM data register 0C51h bits [7:6] to 00b to set GPM port for read */
byte = inb(0xc51);
byte &= 0x3f;
outb(byte, 0xc51);
/* trigger SCI/SMI */
byte = pm_ioread(0x34);
byte &= 0xcf;
pm_iowrite(0x34, byte);
/* set GPM5 to not wake from s5 */
byte = pm_ioread(0x77);
byte &= ~(1 << 5);
pm_iowrite(0x77, byte);
/* trigger on falling edge */
byte = pm_ioread(0x38);
byte &= ~(1 << 2);
pm_iowrite(0x38, byte);
/* set SB600 GPIO 64 to GPIO with pull-up */
byte = pm2_ioread(0x42);
byte &= 0x3f;
pm2_iowrite(0x42, byte);
/* set GPIO 64 to input */
word =
pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x56);
word |= 1 << 7;
pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x56, word);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
byte &= 0xee;
pm2_iowrite(0xf0, byte);
/* set Talert to be active low */
byte = pm_ioread(0x67);
byte &= ~(1 << 5);
pm_iowrite(0x67, byte);
/* set Talert to generate ACPI event */
byte = pm_ioread(0x3c);
byte &= 0xf3;
pm_iowrite(0x3c, byte);
/* THERMTRIP pin */
/* byte = pm_ioread(0x68);
* byte |= 1 << 3;
* pm_iowrite(0x68, byte);
*
* byte = pm_ioread(0x55);
* byte |= 1 << 0;
* pm_iowrite(0x55, byte);
*
* byte = pm_ioread(0x67);
* byte &= ~( 1 << 6);
* pm_iowrite(0x67, byte);
*/
}
/*************************************************
* enable the dedicated function in pistachio board.
* This function called early than rs690_enable.
*************************************************/
void pistachio_enable(device_t dev)
{
struct mainboard_amd_pistachio_config *mainboard =
(struct mainboard_amd_pistachio_config *)dev->chip_info;
printk_info("Mainboard Pistachio Enable. dev=0x%x\n", dev);
#if (CONFIG_GFXUMA == 1)
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
msr = rdmsr(TOP_MEM);
printk_info
("pistachio_enable, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
msr.lo, msr.hi);
/* TOP_MEM2: the top of DRAM above 4G */
msr2 = rdmsr(TOP_MEM2);
printk_info
("pistachio_enable, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
msr2.lo, msr2.hi);
switch (msr.lo) {
case 0x10000000: /* 256M system memory */
uma_memory_size = 0x2000000; /* 32M recommended UMA */
break;
case 0x18000000: /* 384M system memory */
uma_memory_size = 0x4000000; /* 64M recommended UMA */
break;
case 0x20000000: /* 512M system memory */
uma_memory_size = 0x4000000; /* 64M recommended UMA */
break;
default: /* 1GB and above system memory */
uma_memory_size = 0x8000000; /* 128M recommended UMA */
break;
}
uma_memory_start = msr.lo - uma_memory_size; /* TOP_MEM1 */
printk_info("pistachio_enable: uma size 0x%08x, memory start 0x%08x\n",
uma_memory_size, uma_memory_start);
/* TODO: TOP_MEM2 */
#else
uma_memory_size = 0x8000000; /* 128M recommended UMA */
uma_memory_start = 0x38000000; /* 1GB system memory supposed */
#endif
enable_onboard_nic();
set_thermal_config();
}
/*
* CONFIG_CHIP_NAME defined in Option.lb.
*/
struct chip_operations mainboard_amd_pistachio_ops = {
#if CONFIG_CHIP_NAME == 1
CHIP_NAME("AMD pistachio Mainboard")
#endif
.enable_dev = pistachio_enable,
};

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src/mainboard/amd/pistachio/mptable.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
extern u32 apicid_sb600;
extern u32 bus_type[256];
extern u32 sbdn_rs690;
extern u32 sbdn_sb600;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "ATI ";
static const char productid[12] = "PISTACHIO ";
struct mp_config_table *mc;
int j;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
get_bus_conf();
/* Bus: Bus ID Type */
/* define bus and isa numbers */
for (j = 0; j < bus_isa; j++) {
smp_write_bus(mc, j, (char *)"PCI ");
}
smp_write_bus(mc, bus_isa, (char *)"ISA ");
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
u32 dword;
u8 byte;
dev =
dev_find_slot(bus_sb600[0],
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
/* Initialize interrupt mapping */
/* aza */
byte = pci_read_config8(dev, 0x63);
byte &= 0xf8;
byte |= 0; /* 0: INTA, ...., 7: INTH */
pci_write_config8(dev, 0x63, byte);
/* SATA */
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
* 00:12.0: PROG SATA : INT F
* 00:13.0: INTA USB_0
* 00:13.1: INTB USB_1
* 00:13.2: INTC USB_2
* 00:13.3: INTD USB_3
* 00:13.4: INTC USB_4
* 00:13.5: INTD USB2
* 00:14.1: INTA IDE
* 00:14.2: Prog HDA : INT E
* 00:14.5: INTB ACI
* 00:14.6: INTB MCI
*/
}
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb600, 0x0);
/* ISA ints are edge-triggered, and usually originate from the ISA bus,
* or its remainings.
*/
#define ISA_INT(intr, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_sb600, (pin))
ISA_INT(0x1, 0x1);
ISA_INT(0x0, 0x2);
ISA_INT(0x3, 0x3);
ISA_INT(0x4, 0x4);
ISA_INT(0x6, 0x6);
ISA_INT(0x7, 0x7);
ISA_INT(0xc, 0xc);
ISA_INT(0xd, 0xd);
ISA_INT(0xe, 0xe);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if HAVE_ACPI_TABLES == 0
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x13, 0x0, 0x10);
PCI_INT(0x0, 0x13, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x2, 0x12);
PCI_INT(0x0, 0x13, 0x3, 0x13);
/* sata */
PCI_INT(0x0, 0x12, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* on board NIC & Slot PCIE. */
PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v);
}

278
src/mainboard/amd/pistachio/resourcemap.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
static void setup_pistachio_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
/* DRAM Limit i Registers
* F1:0x44 i = 0
* F1:0x4C i = 1
* F1:0x54 i = 2
* F1:0x5C i = 3
* F1:0x64 i = 4
* F1:0x6C i = 5
* F1:0x74 i = 6
* F1:0x7C i = 7
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 7: 3] Reserved
* [10: 8] Interleave select
* specifies the values of A[14:12] to use with interleave enable.
* [15:11] Reserved
* [31:16] DRAM Limit Address i Bits 39-24
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers
* F1:0x40 i = 0
* F1:0x48 i = 1
* F1:0x50 i = 2
* F1:0x58 i = 3
* F1:0x60 i = 4
* F1:0x68 i = 5
* F1:0x70 i = 6
* F1:0x78 i = 7
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 7: 2] Reserved
* [10: 8] Interleave Enable
* 000 = No interleave
* 001 = Interleave on A[12] (2 nodes)
* 010 = reserved
* 011 = Interleave on A[12] and A[14] (4 nodes)
* 100 = reserved
* 101 = reserved
* 110 = reserved
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
* [15:11] Reserved
* [13:16] DRAM Base Address i Bits 39-24
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0
* F1:0x8C i = 1
* F1:0x94 i = 2
* F1:0x9C i = 3
* F1:0xA4 i = 4
* F1:0xAC i = 5
* F1:0xB4 i = 6
* F1:0xBC i = 7
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 3: 3] Reserved
* [ 5: 4] Destination Link ID
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 = Reserved
* [ 6: 6] Reserved
* [ 7: 7] Non-Posted
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
* This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
* F1:0x88 i = 1
* F1:0x90 i = 2
* F1:0x98 i = 3
* F1:0xA0 i = 4
* F1:0xA8 i = 5
* F1:0xB0 i = 6
* F1:0xB8 i = 7
* [ 0: 0] Read Enable
* 0 = Reads disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes disabled
* 1 = Writes Enabled
* [ 2: 2] Cpu Disable
* 0 = Cpu can use this I/O range
* 1 = Cpu requests do not use this I/O range
* [ 3: 3] Lock
* 0 = base/limit registers i are read/write
* 1 = base/limit registers i are read-only
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
* F1:0xCC i = 1
* F1:0xD4 i = 2
* F1:0xDC i = 3
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 3: 3] Reserved
* [ 5: 4] Destination Link ID
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 = reserved
* [11: 6] Reserved
* [24:12] PCI I/O Limit Address i
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
* F1:0xC8 i = 1
* F1:0xD0 i = 2
* F1:0xD8 i = 3
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 3: 2] Reserved
* [ 4: 4] VGA Enable
* 0 = VGA matches Disabled
* 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable
* 0 = ISA matches Disabled
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
* from matching agains this base/limit pair
* [11: 6] Reserved
* [24:12] PCI I/O Base i
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers
* F1:0xE0 i = 0
* F1:0xE4 i = 1
* F1:0xE8 i = 2
* F1:0xEC i = 3
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 2: 2] Device Number Compare Enable
* 0 = The ranges are based on bus number
* 1 = The ranges are ranges of devices on bus 0
* [ 3: 3] Reserved
* [ 6: 4] Destination Node
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 7: 7] Reserved
* [ 9: 8] Destination Link
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 - Reserved
* [15:10] Reserved
* [23:16] Bus Number Base i
* This field defines the lowest bus number in configuration region i
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
};
int max;
max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}

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targets/amd/pistachio/Config-abuild.lb Normal file
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# This will make a target directory of ./VENDOR_MAINBOARD
target VENDOR_MAINBOARD
mainboard VENDOR/MAINBOARD
option CC="CROSSCC"
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
__COMPRESSION__
option ROM_SIZE=1024*1024
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-normal"
payload __PAYLOAD__
end
romimage "failover"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
option COREBOOT_EXTRA_VERSION=".0-failover"
payload __PAYLOAD__
end
buildrom ./coreboot.rom ROM_SIZE "normal" "failover"

21
targets/amd/pistachio/Config.lb Normal file
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# This will make a target directory of ./pistachio
target pistachio
mainboard amd/pistachio
romimage "normal"
option ROM_SIZE = 1024*1024 - 55808
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
payload ../payload.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x20000
option XIP_ROM_SIZE=0x20000
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"