diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index 9604210794..e5f867cbdc 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -5,7 +5,7 @@ chip soc/intel/cannonlake
 	end
 
 	# FSP configuration
-	register "SaGv" = "SaGv_FixedHigh"
+	register "SaGv" = "SaGv_Enabled"
 	register "ScsEmmcHs400Enabled" = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index e2ebaba1cb..a6d329be82 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -5,7 +5,7 @@ chip soc/intel/cannonlake
 	end
 
 	# FSP configuration
-	register "SaGv" = "SaGv_FixedHigh"
+	register "SaGv" = "SaGv_Enabled"
 	register "ScsEmmcHs400Enabled" = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"