Add support for the Traverse Technologies Geos mainboard.
This board is similar to the AMD Norwich mainboard. Signed-off-by: Nathan Williams <nathan@traverse.com.au> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nathan Williams
Stefan Reinauer
parent
6d77252e74
commit
1a169d2a46
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@ -96,6 +96,8 @@ config VENDOR_TELEVIDEO
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bool "TeleVideo"
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config VENDOR_THOMSON
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bool "Thomson"
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config VENDOR_TRAVERSE
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bool "Traverse Technologies"
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config VENDOR_TYAN
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bool "Tyan"
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config VENDOR_VIA
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@ -357,6 +359,11 @@ config MAINBOARD_VENDOR
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default "Thomson"
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depends on VENDOR_THOMSON
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config MAINBOARD_VENDOR
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string
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default "Traverse Technologies"
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depends on VENDOR_TRAVERSE
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config MAINBOARD_VENDOR
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string
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default "Tyan"
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@ -438,6 +445,7 @@ source "src/mainboard/technexion/Kconfig"
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source "src/mainboard/technologic/Kconfig"
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source "src/mainboard/televideo/Kconfig"
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source "src/mainboard/thomson/Kconfig"
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source "src/mainboard/traverse/Kconfig"
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source "src/mainboard/tyan/Kconfig"
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source "src/mainboard/via/Kconfig"
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source "src/mainboard/winent/Kconfig"
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@ -0,0 +1,7 @@
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choice
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prompt "Mainboard model"
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depends on VENDOR_TRAVERSE
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source "src/mainboard/traverse/geos/Kconfig"
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endchoice
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@ -0,0 +1,37 @@
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config BOARD_TRAVERSE_GEOS
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bool "Geos"
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select ARCH_X86
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select CPU_AMD_LX
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select NORTHBRIDGE_AMD_LX
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select SOUTHBRIDGE_AMD_CS5536
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select HAVE_PIRQ_TABLE
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select PIRQ_ROUTE
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select UDELAY_TSC
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select USE_DCACHE_RAM
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select USE_PRINTK_IN_CAR
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select BOARD_ROMSIZE_KB_1024
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config MAINBOARD_DIR
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string
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default traverse/geos
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depends on BOARD_TRAVERSE_GEOS
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config MAINBOARD_PART_NUMBER
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string
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default "Geos"
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depends on BOARD_TRAVERSE_GEOS
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config HAVE_OPTION_TABLE
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bool
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default n
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depends on BOARD_TRAVERSE_GEOS
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config IRQ_SLOT_COUNT
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int
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default 6
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depends on BOARD_TRAVERSE_GEOS
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config RAMBASE
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hex
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default 0x4000
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depends on BOARD_TRAVERSE_GEOS
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@ -0,0 +1,25 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {
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int nothing;
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};
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@ -0,0 +1,75 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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440 1 e 0 dcon_present
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1008 16 h 0 check_sum
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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checksums
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checksum 392 1007 1008
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@ -0,0 +1,40 @@
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chip northbridge/amd/lx
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device pci_domain 0 on
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device pci 1.0 on end # Northbridge
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device pci 1.1 on end # Graphics
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chip southbridge/amd/cs5536
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# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
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# SIRQ Mode = Active(Quiet) mode. Save power....
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
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register "lpc_serirq_enable" = "0x00001002"
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register "lpc_serirq_polarity" = "0x0000EFFD"
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register "lpc_serirq_mode" = "1"
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register "enable_gpio_int_route" = "0x0D0C0700"
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register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
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register "enable_USBP4_device" = "0" #0: host, 1:device
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register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
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register "com1_enable" = "1"
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register "com1_address" = "0x3F8"
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register "com1_irq" = "4"
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register "com2_enable" = "0"
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register "com2_address" = "0x2F8"
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register "com2_irq" = "3"
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register "unwanted_vpci[0]" = "0" # End of list has a zero
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device pci a.0 on end # Ethernet 0
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device pci b.0 on end # Ethernet 1
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device pci c.0 on end # Xilinx
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device pci d.0 on end # Mini PCI
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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# APIC cluster is late CPU init.
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device lapic_cluster 0 on
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chip cpu/amd/model_lx
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device lapic 0 on end
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end
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end
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end
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@ -0,0 +1,71 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/pirq_routing.h>
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#include "../../../southbridge/amd/cs5536/cs5536.h"
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/* Platform IRQs */
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#define PIRQA 11
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#define PIRQB 10
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#define PIRQC 11
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#define PIRQD 9
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/* Map */
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#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
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#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
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#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
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#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
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/* Link */
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#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
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#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
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#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
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#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
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0x00, /* IRQs devoted exclusively to PCI usage */
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0x100B, /* Vendor */
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0x002B, /* Device */
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0, /* Crap (miniport) */
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
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0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
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{0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth0 */
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{0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth1 */
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{0x00, (0x0C << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x2, 0x0}, /* xilinx */
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{0x00, (0x0D << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}}, 0x1, 0x0}, /* mini PCI */
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{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -0,0 +1,38 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include "chip.h"
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static void init(struct device *dev)
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{
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printk(BIOS_DEBUG, "Geos ENTER %s\n", __func__);
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printk(BIOS_DEBUG, "Geos EXIT %s\n", __func__);
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}
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static void enable_dev(struct device *dev)
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{
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dev->ops->init = init;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME("Traverse Technologies Geos Mainboard")
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.enable_dev = enable_dev,
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};
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@ -0,0 +1,100 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/hlt.h>
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#include <console/console.h>
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#include "lib/ramtest.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/lxdef.h>
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#include <cpu/amd/geode_post_code.h>
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#include "southbridge/amd/cs5536/cs5536.h"
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#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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static inline int spd_read_byte(unsigned int device, unsigned int address)
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{
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return smbus_read_byte(device, address);
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}
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#define ManualConf 1 /* Do automatic strapped PLL config */
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#define PLLMSRhi 0x0000059C /* manual settings for the PLL */
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#define PLLMSRlo 0x00DE602E
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#define DIMM0 0xA0
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#define DIMM1 0xA2
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#include "northbridge/amd/lx/raminit.h"
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#include "northbridge/amd/lx/pll_reset.c"
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#include "northbridge/amd/lx/raminit.c"
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#include "lib/generic_sdram.c"
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#include "cpu/amd/model_lx/cpureginit.c"
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#include "cpu/amd/model_lx/syspreinit.c"
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#include "cpu/amd/model_lx/msrinit.c"
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static void mb_gpio_init(void)
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{
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/* Early mainboard specific GPIO setup. */
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}
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void main(unsigned long bist)
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{
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post_code(0x01);
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static const struct mem_controller memctrl[] = {
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{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
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};
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SystemPreInit();
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msr_init();
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cs5536_early_setup();
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/* Note: must do this AFTER the early_setup! It is counting on some
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* early MSR setup for CS5536.
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*/
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/* cs5536_disable_internal_uart: disable them for now, set them
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* up later...
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*/
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/* If debug. real setup done in chipset init via Config.lb. */
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cs5536_setup_onchipuart(1);
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mb_gpio_init();
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uart_init();
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console_init();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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pll_reset(ManualConf);
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cpuRegInit();
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sdram_initialize(1, memctrl);
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/* Check memory. */
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/* ram_check(0x00000000, 640 * 1024); */
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/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
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return;
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}
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