GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mips: implement arch_segment_loaded callback 

This change adds cache management after loading stages.
Before jumping to a new stage we should flush the data
caches to memory and invalidate instruction cache.
After all segments are loaded CBFS cache is also
flushed.

With this change all stages of coreboot are now executed
successfully. This was tested on Pistachio bring up board,
also known as Urara.

Change-Id: I86e07432c21a803ef1cfc41b633c5df42b99de90
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: http://review.coreboot.org/10456
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Ionela Voinescu 2015-05-20 17:03:23 +01:00 committed by Patrick Georgi
parent 82efc7600a
commit 1a1a826276
1 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/arch/mips/cache.c
View File

@ -20,6 +20,7 @@
#include <arch/cache.h> #include <arch/cache.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <console/console.h> #include <console/console.h>
#include <program_loading.h>
#include <symbols.h> #include <symbols.h>
/* cache_op: issues cache operation for specified address */ /* cache_op: issues cache operation for specified address */
@ -109,3 +110,10 @@ void cache_invalidate_all(uintptr_t start, size_t size)
perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD)); perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD));
perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD)); perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD));
} }
void arch_segment_loaded(uintptr_t start, size_t size, int flags)
{
cache_invalidate_all(start, size);
if (flags & SEG_FINAL)
cache_invalidate_all((uintptr_t)_cbfs_cache, _cbfs_cache_size);
}