From 1a1f00cf413df295186a226150ca82d1f5d7ee23 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Sat, 8 Dec 2018 12:00:17 -0800 Subject: [PATCH] mb/google/sarien: Setup GPIOs again after FSP-S Currently CoffeeLake FSP is incorrectly modifying GPIO pad configuration if specific UPD variables are not set as it expects. This affects the display-related SOC pads with the following UPD variables: UINT8 DdiPortBHpd; // GPP_E13 UINT8 DdiPortCHpd; // GPP_E14 UINT8 DdiPortDHpd; // GPP_E15 UINT8 DdiPortFHpd; // GPP_E16 UINT8 DdiPortBDdc; // GPP_E18/GPP_E19 UINT8 DdiPortCDdc; // GPP_E20/GPP_E21 UINT8 DdiPortDDdc; // GPP_E22/GPP_E23 UINT8 DdiPortFDdc; // GPP_H16/GPP_H17 Until FSP is fixed to not touch the pad configuration this workaround will reprogram the GPIO settings after FSP-S step so they are correct when the OS attempts to use them. This was found in CoffeLake FSP Gold release: https://github.com/IntelFsp/FSP/tree/master/CoffeeLakeFspBinPkg As well as the current top-of-tree for the FSP sources. BUG=b:120686247,chromium:913216 TEST=verify correct GPIO configuration for GPP_E group in the kernel Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/30113 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao Reviewed-by: Furquan Shaikh --- src/mainboard/google/sarien/ramstage.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index c65104be8b..c2dc27daee 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -27,8 +27,19 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) gpio_configure_pads(gpio_table, num_gpios); } +/* Workaround FSP issue by reprogramming GPIOs after FSP-S */ +static void mainboard_init(struct device *dev) +{ + const struct pad_config *gpio_table; + size_t num_gpios; + + gpio_table = variant_gpio_table(&num_gpios); + gpio_configure_pads(gpio_table, num_gpios); +} + static void mainboard_enable(struct device *dev) { + dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; }