soc/amd/common/psp_verstage: Write postcodes after ESPI init
On boards where PSP uses ESPI to write postcodes, update the verstage to do it after ESPI initialization. BUG=b:224543620 TEST=Build and boot to OS in Nipperkin. Ensure that there are no attempts to write the post code from PSP verstage before ESPI initialization. Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mohan Viswanathan Reviewed-by: Raul Rangel <rrangel@chromium.org>
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@ -345,6 +345,14 @@ config PSP_DISABLE_POSTCODES
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help
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Disables the output of port80 post codes from PSP.
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config PSP_POSTCODES_ON_ESPI
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bool "Use eSPI bus for PSP post codes"
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depends on !PSP_DISABLE_POSTCODES
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default y
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help
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Select to send PSP port80 post codes on eSPI bus.
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If not selected, PSP port80 codes will be sent on LPC bus.
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config PSP_INIT_ESPI
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bool "Initialize eSPI in PSP Stage 2 Boot Loader"
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help
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@ -206,16 +206,21 @@ void Main(void)
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/*
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* Do not use printk() before console_init()
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* Do not use post_code() before verstage_mainboard_init()
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* Do not use svc_write_postcode before verstage_soc_espi_init() if PSP uses ESPI
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* to write postcodes.
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*/
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timestamp_init(timestamp_get());
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svc_write_postcode(POSTCODE_ENTERED_PSP_VERSTAGE);
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if (!CONFIG(PSP_POSTCODES_ON_ESPI))
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svc_write_postcode(POSTCODE_ENTERED_PSP_VERSTAGE);
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svc_debug_print("Entering verstage on PSP\n");
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memset(&_bss_start, '\0', &_bss_end - &_bss_start);
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svc_write_postcode(POSTCODE_CONSOLE_INIT);
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if (!CONFIG(PSP_POSTCODES_ON_ESPI))
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svc_write_postcode(POSTCODE_CONSOLE_INIT);
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console_init();
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svc_write_postcode(POSTCODE_EARLY_INIT);
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if (!CONFIG(PSP_POSTCODES_ON_ESPI))
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svc_write_postcode(POSTCODE_EARLY_INIT);
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retval = verstage_soc_early_init();
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if (retval) {
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/*
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