soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors

Add fan based active cooling for TSR sensors temperature range.

BUG=b:138966929
BRANCH=None
TEST=Verified Fan control functionality for TSR sensors on Hatch.

Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet Pawnikar 2019-08-27 18:32:58 +05:30 committed by Furquan Shaikh
parent 809b7513a2
commit 1a29f4aeeb
1 changed files with 180 additions and 0 deletions

View File

@ -155,6 +155,51 @@ Device (TSR0)
{
\_SB.PCI0.LPCB.EC0.PATD (TMPI)
}
#ifdef DPTF_ENABLE_FAN_CONTROL
#ifdef DPTF_TSR0_ACTIVE_AC0
Method (_AC0)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0))
}
#endif
#ifdef DPTF_TSR0_ACTIVE_AC1
Method (_AC1)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1))
}
#endif
#ifdef DPTF_TSR0_ACTIVE_AC2
Method (_AC2)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2))
}
#endif
#ifdef DPTF_TSR0_ACTIVE_AC3
Method (_AC3)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3))
}
#endif
#ifdef DPTF_TSR0_ACTIVE_AC4
Method (_AC4)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4))
}
#endif
#ifdef DPTF_TSR0_ACTIVE_AC5
Method (_AC5)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5))
}
#endif
#ifdef DPTF_TSR0_ACTIVE_AC6
Method (_AC6)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6))
}
#endif
#endif
}
#endif
@ -219,6 +264,51 @@ Device (TSR1)
{
\_SB.PCI0.LPCB.EC0.PATD (TMPI)
}
#ifdef DPTF_ENABLE_FAN_CONTROL
#ifdef DPTF_TSR1_ACTIVE_AC0
Method (_AC0)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
}
#endif
#ifdef DPTF_TSR1_ACTIVE_AC1
Method (_AC1)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
}
#endif
#ifdef DPTF_TSR1_ACTIVE_AC2
Method (_AC2)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
}
#endif
#ifdef DPTF_TSR1_ACTIVE_AC3
Method (_AC3)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
}
#endif
#ifdef DPTF_TSR1_ACTIVE_AC4
Method (_AC4)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
}
#endif
#ifdef DPTF_TSR1_ACTIVE_AC5
Method (_AC5)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC5))
}
#endif
#ifdef DPTF_TSR1_ACTIVE_AC6
Method (_AC6)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC6))
}
#endif
#endif
}
#endif
@ -283,6 +373,51 @@ Device (TSR2)
{
\_SB.PCI0.LPCB.EC0.PATD (TMPI)
}
#ifdef DPTF_ENABLE_FAN_CONTROL
#ifdef DPTF_TSR2_ACTIVE_AC0
Method (_AC0)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC0))
}
#endif
#ifdef DPTF_TSR2_ACTIVE_AC1
Method (_AC1)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC1))
}
#endif
#ifdef DPTF_TSR2_ACTIVE_AC2
Method (_AC2)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC2))
}
#endif
#ifdef DPTF_TSR2_ACTIVE_AC3
Method (_AC3)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC3))
}
#endif
#ifdef DPTF_TSR2_ACTIVE_AC4
Method (_AC4)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC4))
}
#endif
#ifdef DPTF_TSR2_ACTIVE_AC5
Method (_AC5)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC5))
}
#endif
#ifdef DPTF_TSR2_ACTIVE_AC6
Method (_AC6)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC6))
}
#endif
#endif
}
#endif
@ -347,5 +482,50 @@ Device (TSR3)
{
\_SB.PCI0.LPCB.EC0.PATD (TMPI)
}
#ifdef DPTF_ENABLE_FAN_CONTROL
#ifdef DPTF_TSR3_ACTIVE_AC0
Method (_AC0)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC0))
}
#endif
#ifdef DPTF_TSR3_ACTIVE_AC1
Method (_AC1)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC1))
}
#endif
#ifdef DPTF_TSR3_ACTIVE_AC2
Method (_AC2)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC2))
}
#endif
#ifdef DPTF_TSR3_ACTIVE_AC3
Method (_AC3)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC3))
}
#endif
#ifdef DPTF_TSR3_ACTIVE_AC4
Method (_AC4)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC4))
}
#endif
#ifdef DPTF_TSR3_ACTIVE_AC5
Method (_AC5)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC5))
}
#endif
#ifdef DPTF_TSR3_ACTIVE_AC6
Method (_AC6)
{
Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC6))
}
#endif
#endif
}
#endif