GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

southbridge/amd/sb700: Fix boot hang when AHCI mode disabled 

Existence of requested PCI device was not checked when enabling
IDE mode on the SP5100.  Fix incorrect PCI device ID and check
for device existence before attempting setup.

Change-Id: I726c355571b5c67c9a13995be2352601c03ab1e4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12572
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2015-10-25 18:58:24 -05:00 committed by Martin Roth
parent 273384638b
commit 1a38374535
1 changed files with 17 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
src/southbridge/amd/sb700/early_setup.c
View File

@ -520,26 +520,28 @@ static void sb700_devices_por_init(void)
if (!sata_ahci_mode){ if (!sata_ahci_mode){
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
/* SP5100 default SATA mode is RAID5 MODE */ /* SP5100 default SATA mode is RAID5 MODE */
dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0); dev = pci_locate_device(PCI_ID(0x1002, 0x4392), 0);
/* Set SATA Operation Mode, Set to IDE mode */ if (dev != PCI_DEV_INVALID) {
byte = pci_read_config8(dev, 0x40); /* Set SATA Operation Mode, Set to IDE mode */
byte |= (1 << 0); byte = pci_read_config8(dev, 0x40);
pci_write_config8(dev, 0x40, byte); byte |= (1 << 0);
pci_write_config8(dev, 0x40, byte);
dword = 0x01018f00; dword = 0x01018f00;
pci_write_config32(dev, 0x8, dword); pci_write_config32(dev, 0x8, dword);
/* set SATA Device ID writable */ /* set SATA Device ID writable */
dword = pci_read_config32(dev, 0x40); dword = pci_read_config32(dev, 0x40);
dword &= ~(1 << 24); dword &= ~(1 << 24);
pci_write_config32(dev, 0x40, dword); pci_write_config32(dev, 0x40, dword);
/* set Device ID consistent with IDE emulation mode configuration */ /* set Device ID consistent with IDE emulation mode configuration */
pci_write_config32(dev, 0x0, 0x43901002); pci_write_config32(dev, 0x0, 0x43901002);
/* rpr v2.13 4.17 Reset CPU on Sync Flood */ /* rpr v2.13 4.17 Reset CPU on Sync Flood */
abcfg_reg(0x10050, 1 << 2, 1 << 2); abcfg_reg(0x10050, 1 << 2, 1 << 2);
}
#endif #endif
} }