soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncar
The same functionality will eventually be needed on Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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@ -2,6 +2,7 @@
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#include <amdblocks/memmap.h>
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#include <amdblocks/smm.h>
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#include <arch/bert_storage.h>
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#include <console/console.h>
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#include <cbmem.h>
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#include <cpu/amd/msr.h>
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@ -58,3 +59,22 @@ void smm_region(uintptr_t *start, size_t *size)
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once = 1;
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}
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}
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void bert_reserved_region(void **start, size_t *size)
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{
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struct range_entry bert;
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int status;
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*start = NULL;
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*size = 0;
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status = fsp_find_range_hob(&bert, AMD_FSP_BERT_HOB_GUID.b);
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if (status < 0) {
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printk(BIOS_ERR, "Error: unable to find BERT HOB\n");
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return;
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}
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*start = (void *)(uintptr_t)range_entry_base(&bert);
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*size = range_entry_size(&bert);
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}
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@ -23,7 +23,6 @@ romstage-y += i2c.c
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romstage-y += romstage.c
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romstage-y += gpio.c
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romstage-y += reset.c
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romstage-y += memmap.c
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romstage-y += uart.c
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romstage-y += mrc_cache.c
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@ -45,7 +44,6 @@ ramstage-y += fch.c
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ramstage-y += reset.c
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ramstage-y += acp.c
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ramstage-y += sata.c
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ramstage-y += memmap.c
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ramstage-y += uart.c
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ramstage-y += finalize.c
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ramstage-y += soc_util.c
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@ -1,28 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <stdint.h>
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#include <console/console.h>
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#include <arch/bert_storage.h>
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#include <memrange.h>
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#include <fsp/util.h>
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#include <FspGuids.h>
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void bert_reserved_region(void **start, size_t *size)
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{
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struct range_entry bert;
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int status;
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*start = NULL;
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*size = 0;
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status = fsp_find_range_hob(&bert, AMD_FSP_BERT_HOB_GUID.b);
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if (status < 0) {
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printk(BIOS_ERR, "Error: unable to find BERT HOB\n");
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return;
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}
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*start = (void *)(uintptr_t)range_entry_base(&bert);
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*size = range_entry_size(&bert);
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}
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