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mb/google/zork/var/vliboz: Add LTE_RST power sequence 

Latest HW schematic add LTE_RST pin to control module power sequence.

BUG=b:173490220
BRANCH=zork
TEST=measure the waveform is meet the LTE module spec.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Eric Lai 2020-11-24 22:30:52 +08:00 committed by Patrick Georgi
parent 6c38f35da3
commit 1a3ae36c6a
1 changed files with 2 additions and 0 deletions
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2
src/mainboard/google/zork/variants/vilboz/gpio.c
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@ -19,6 +19,8 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = { static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = {
/* P sensor INT */ /* P sensor INT */
PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY), PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY),
/* LTE_RST_L */
PAD_GPO(GPIO_89, HIGH),
}; };
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)