From 1a4abb73cdeae498e1470d273fee7cc1f35912e7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 19 May 2018 16:49:20 +0200 Subject: [PATCH] sb/amd/cimx/sb800: Get rid of device_t MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use of device_t has been abandoned in ramstage. Change-Id: I2335b7e193663bb6c82bf267aaeb0b2367986f62 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/26414 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/amd/cimx/sb800/fan.c | 6 +++--- src/southbridge/amd/cimx/sb800/fan.h | 4 ++-- src/southbridge/amd/cimx/sb800/late.c | 8 ++++---- src/southbridge/amd/cimx/sb800/lpc.c | 6 +++--- src/southbridge/amd/cimx/sb800/lpc.h | 6 +++--- src/southbridge/amd/cimx/sb800/spi.c | 2 +- 6 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index 5925330f11..977ffb6f62 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -14,14 +14,14 @@ */ #include -#include /* device_t */ +#include #include /* device_operations */ #include "SBPLATFORM.h" #include "sb_cimx.h" #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ #include "fan.h" -void init_sb800_MANUAL_fans(device_t dev) +void init_sb800_MANUAL_fans(struct device *dev) { int i; struct southbridge_amd_cimx_sb800_config *sb_chip = @@ -54,7 +54,7 @@ void init_sb800_MANUAL_fans(device_t dev) } -void init_sb800_IMC_fans(device_t dev) +void init_sb800_IMC_fans(struct device *dev) { AMDSBCFG sb_config; diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h index 6542967d67..f31e48645e 100644 --- a/src/southbridge/amd/cimx/sb800/fan.h +++ b/src/southbridge/amd/cimx/sb800/fan.h @@ -17,8 +17,8 @@ #define _SB800_FAN_H_ #ifndef __PRE_RAM__ -void init_sb800_IMC_fans(device_t dev); -void init_sb800_MANUAL_fans(device_t dev); +void init_sb800_IMC_fans(struct device *dev); +void init_sb800_MANUAL_fans(struct device *dev); #endif /* Fan Register Definitions */ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 393eda0090..fb5dadd7df 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -15,7 +15,7 @@ */ -#include /* device_t */ +#include #include /* device_operations */ #include #include @@ -118,7 +118,7 @@ static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); @@ -344,7 +344,7 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); /** * @brief SB Cimx entry point sbBeforePciInit wrapper */ -static void sb800_enable(device_t dev) +static void sb800_enable(struct device *dev) { struct southbridge_amd_cimx_sb800_config *sb_chip = (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); @@ -427,7 +427,7 @@ static void sb800_enable(device_t dev) case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ { - device_t device; + struct device *device; for (device = dev; device; device = device->sibling) { if ((device->path.pci.devfn & ~3) != PCI_DEVFN(0x15,0)) break; sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 49735583cc..40c0739bb1 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -22,7 +22,7 @@ #include #include -void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res; @@ -76,7 +76,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whose children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -88,7 +88,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index ee76b43a44..b478eb40a7 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -21,8 +21,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 -void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev); #endif diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 2c541e352e..54dd77a729 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -48,7 +48,7 @@ static void execute_command(void) void spi_init() { - device_t dev; + struct device *dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F;