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cpu/amd: Use common AMD's MSR

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This Phase #2 follows the CL done on Phase #1 (Change-Id: I0236e0960cd)

Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29369
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2018-10-31 08:06:12 +01:00 committed by Patrick Georgi
parent d35c7fe1bf
commit 1a5f1c89d7
3 changed files with 8 additions and 5 deletions
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8
src/cpu/amd/car/cache_as_ram.inc
View file

@ -415,26 +415,26 @@ fam10_mtrr_setup_complete:
jmp_if_not_fam15h(fam15_car_msr_setup_complete) jmp_if_not_fam15h(fam15_car_msr_setup_complete)
/* Disable streaming store (DisSS = 1) */ /* Disable streaming store (DisSS = 1) */
mov $0xc0011020, %ecx mov $LS_CFG_MSR, %ecx
rdmsr rdmsr
bts $28, %eax bts $28, %eax
wrmsr wrmsr
/* Disable speculative ITLB reloads (DisSpecTlbRld = 1) */ /* Disable speculative ITLB reloads (DisSpecTlbRld = 1) */
mov $0xc0011021, %ecx mov $IC_CFG_MSR, %ecx
rdmsr rdmsr
bts $9, %eax bts $9, %eax
wrmsr wrmsr
/* Disable speculative DTLB reloads (DisSpecTlbRld = 1) and set DisHwPf = 1 */ /* Disable speculative DTLB reloads (DisSpecTlbRld = 1) and set DisHwPf = 1 */
mov $0xc0011022, %ecx mov $DC_CFG_MSR, %ecx
rdmsr rdmsr
bts $4, %eax bts $4, %eax
bts $13, %eax bts $13, %eax
wrmsr wrmsr
/* Disable CR0 combining (CombineCr0Cd = 0) */ /* Disable CR0 combining (CombineCr0Cd = 0) */
mov $0xc001102b, %ecx mov $BU_CFG3_MSR, %ecx
rdmsr rdmsr
btr $49-32, %edx btr $49-32, %edx
wrmsr wrmsr

3
src/cpu/amd/microcode/microcode.c
View file

@ -17,6 +17,7 @@
#include <stdint.h> #include <stdint.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/microcode.h> #include <cpu/amd/microcode.h>
#include <cbfs.h> #include <cbfs.h>
#include <arch/io.h> #include <arch/io.h>
@ -121,7 +122,7 @@ static void apply_microcode_patch(const struct microcode *m)
msr.hi = 0; msr.hi = 0;
msr.lo = (uint32_t)m; msr.lo = (uint32_t)m;
wrmsr(0xc0010020, msr); wrmsr(MSR_PATCH_LOADER, msr);
UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id); UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);

2
src/include/cpu/amd/msr.h
View file

@ -58,6 +58,8 @@
#define PSTATE_3_MSR 0xC0010067 #define PSTATE_3_MSR 0xC0010067
#define PSTATE_4_MSR 0xC0010068 #define PSTATE_4_MSR 0xC0010068
#define MSR_PATCH_LOADER 0xC0010020
#define MSR_COFVID_STS 0xC0010071 #define MSR_COFVID_STS 0xC0010071
#define MSR_CSTATE_ADDRESS 0xC0010073 #define MSR_CSTATE_ADDRESS 0xC0010073
#define OSVW_ID_Length 0xC0010140 #define OSVW_ID_Length 0xC0010140