diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index e0d3beaaa2..0e8ad3e17a 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -211,15 +211,25 @@ chip soc/intel/tigerlake
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
+	register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 38,
+		.tdp_pl4 = 71,
+	}"
 	register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 60,
 		.tdp_pl4 = 105,
 	}"
-	register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
-		.tdp_pl1_override = 15,
-		.tdp_pl2_override = 38,
-		.tdp_pl4 = 71,
+	register "power_limits_config[POWER_LIMITS_Y_2_CORE]" = "{
+		.tdp_pl1_override = 9,
+		.tdp_pl2_override = 35,
+		.tdp_pl4 = 66,
+	}"
+	register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{
+		.tdp_pl1_override = 9,
+		.tdp_pl2_override = 40,
+		.tdp_pl4 = 83,
 	}"
 
 	register "Device4Enable" = "1"
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 59dab58bb8..3d910cee94 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -23,9 +23,11 @@
 #define MAX_HD_AUDIO_SSP_LINKS  6
 
 /* The first two are for TGL-U */
-#define POWER_LIMITS_U_4_CORE	0
-#define POWER_LIMITS_U_2_CORE	1
-#define POWER_LIMITS_MAX	2
+#define POWER_LIMITS_U_2_CORE	0
+#define POWER_LIMITS_U_4_CORE	1
+#define POWER_LIMITS_Y_2_CORE	2
+#define POWER_LIMITS_Y_4_CORE	3
+#define POWER_LIMITS_MAX	4
 
 /*
  * Enable External V1P05 Rail in: BIT0:S0i1/S0i2,
diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c
index fd611bbd1c..29487a8c81 100644
--- a/src/soc/intel/tigerlake/systemagent.c
+++ b/src/soc/intel/tigerlake/systemagent.c
@@ -84,6 +84,12 @@ void soc_systemagent_init(struct device *dev)
 	case PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2:
 		soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE];
 		break;
+	case PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2:
+		soc_config = &config->power_limits_config[POWER_LIMITS_Y_2_CORE];
+		break;
+	case PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2:
+		soc_config = &config->power_limits_config[POWER_LIMITS_Y_4_CORE];
+		break;
 	default:
 		printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits "
 		       "configuration\n", sa_pci_id);