diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S
index a1a1b156db..2dc533ac53 100644
--- a/src/northbridge/intel/i5000/halt_second_bsp.S
+++ b/src/northbridge/intel/i5000/halt_second_bsp.S
@@ -2,6 +2,26 @@
 
 	movl	%eax, %ebp
 
+	/* check if SPAD0 is cleared. If yes, it means this was a hard reset */
+	movl	$0x800080d0, %eax
+	movw	$0xcf8, %dx
+	outl	%eax, %dx
+
+	addw	$4, %dx
+	inl	%dx, %eax
+	cmp	$0, %eax
+	je	no_reset
+
+	/* perform hard reset */
+	movw	$0xcf9, %dx
+	movw	$0x06, %ax
+	outw	%ax, %dx
+
+loop0:	hlt
+	jmp	loop
+
+no_reset:
+
 	/* Read the semaphore register of i5000 (BOFL0).
 	   If it returns zero, it means there was already
 	   another read by another CPU */
@@ -25,5 +45,14 @@
 loop:	hlt
 	jmp	loop
 
-1:	/* Restore BIST */
+1:	/* set magic value for soft reset detection */
+	movl    $0x800080d0, %eax
+	movw    $0xcf8, %dx
+	outl    %eax, %dx
+
+	addw    $4, %dx
+	movl	$0x12345678, %eax
+	outl	%eax, %dx
+
+	/* Restore BIST */
 	mov	%ebp, %eax