mb/google/rex/variants/ovis: Add I2C config

BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I1644b1d8f49accbb2ea68e236534df80a5151360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75503
Reviewed-by: Jan Dabros <dabros@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/mainboard/google/rex/variants/ovis/overridetree.cb

@@ -1,4 +1,39 @@
 chip soc/intel/meteorlake
+
+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoPci,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C4              | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.i2c[4] = {
+			.early_init = 1,
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 600,
+			.fall_time_ns = 400,
+			.data_hold_time_ns = 50,
+		},
+	}"
+
 	device domain 0 on
+		device ref i2c4 on
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E03_IRQ)"
+				device i2c 50 on end
+			end
+		end
 	end
 end