mb/intel/mtlrvp: Enable ACPI support for Type-C ports
This patch adds ACPI support for Type-C ports. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP. Verify SSDT for the corresponding entry, \_SB.PCI0.PMC.MUX.CON0 under Device (CON0) \_SB.PCI0.PMC.MUX.CON1 under Device (CON1) \_SB.PCI0.PMC.MUX.CON2 under Device (CON2) \_SB.PCI0.PMC.MUX.CON3 under Device (CON3) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72789 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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@ -13,6 +13,7 @@ config BOARD_INTEL_MTLRVP_P
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config BOARD_INTEL_MTLRVP_P_EXT_EC
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select BOARD_INTEL_MTLRVP_COMMON
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select DRIVERS_INTEL_PMC
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if BOARD_INTEL_MTLRVP_COMMON
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@ -22,6 +22,7 @@ DefinitionBlock(
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/meteorlake/acpi/southbridge.asl>
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#include <soc/intel/meteorlake/acpi/tcss.asl>
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}
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}
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@ -3,8 +3,38 @@ chip soc/intel/meteorlake
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device domain 0 on
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device ref soc_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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use conn2 as mux_conn[2]
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use conn3 as mux_conn[3]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port2 as usb2_port
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use tcss_usb3_port2 as usb3_port
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device generic 1 alias conn1 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port3 as usb2_port
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use tcss_usb3_port3 as usb3_port
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device generic 2 alias conn2 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port4 as usb2_port
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use tcss_usb3_port4 as usb3_port
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device generic 3 alias conn3 on end
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end
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end
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end
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end
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end
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end
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