diff --git a/src/northbridge/intel/i945/errata.c b/src/northbridge/intel/i945/errata.c
index 3057ae92e2..c4219d94e3 100644
--- a/src/northbridge/intel/i945/errata.c
+++ b/src/northbridge/intel/i945/errata.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <stdint.h>
+
 #include "i945.h"
 #include "raminit.h"
 
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index d8993acdf0..3470a77eee 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -3,10 +3,11 @@
 #ifndef NORTHBRIDGE_INTEL_I945_H
 #define NORTHBRIDGE_INTEL_I945_H
 
-#define DEFAULT_X60BAR		0xfed13000
-
+#include <northbridge/intel/common/fixed_bars.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 
+#define DEFAULT_X60BAR		0xfed13000
+
 /* Everything below this line is ignored in the DSDT */
 #ifndef __ACPI__
 
@@ -86,12 +87,6 @@
 #define BSM		0x5c
 #define GCFC		0xf0	/* Graphics Clock Frequency & Gating Control */
 
-/*
- * MCHBAR
- */
-
-#include <northbridge/intel/common/fixed_bars.h>
-
 /* Chipset Control Registers */
 #define FSBPMC3		0x40	/* 32bit */
 #define FSBPMC4		0x44	/* 32bit */
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c
index 0a61780cdc..61b9bcff43 100644
--- a/src/northbridge/intel/i945/romstage.c
+++ b/src/northbridge/intel/i945/romstage.c
@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stdint.h>
-#include <cf9_reset.h>
 #include <arch/romstage.h>
+#include <cf9_reset.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
-#include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/pmclib.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <stdint.h>
 
 __weak void mainboard_lpc_decode(void)
 {