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soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDs 

SataPortsEnableDitoConfig Enable DEVSLP Idle Timeout settings DmVal and
DitoVal. SataPortsDmVal and SataPortsDitoVal helps to determine when to
enter Device Sleep. Device Sleep enables the host bus adapter (HBA) to
assert the DEVSLP signal as soon as there are no commands outstanding
to the device and the port specific Device Sleep idle timer has expired.
Device Sleep Idle Timeout values (PxDEVSLP.DITO and PxDEVSLP.DM) are
port specific timeout values used by the HBA for determining when to
assert the DEVSLP signal. They provides a mechanism for the HBA to apply
a programmable amount of hysteresis so as to prevent the HBA from
asserting the DEVSLP signal too quickly which may result in undesirable
latencies. This patch is created based on Intel Tiger Lake Processor
PCH Datasheet with Document number:575857 and Chapter number:12.

* PxDEVSLP.DM ->     SataPortsDmVal: Enable SATA Port DmVal DITO multiplier.
 Default is 15.
* PxDEVSLP.DITO -> SataPortsDitoVal: Enable SATA Port DmVal DEVSLP Idle Timeout
 (DITO), Default is 625ms.

BUG=b:151163106
BRANCH=None
TEST=Build and boot volteer and TGL RVP.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I6a824524738a9e0609f54bea9d892b4a42a1d3db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42214
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shaunak Saha 2020-06-08 18:59:47 -07:00 committed by Patrick Georgi
parent 742abd3daf
commit 1a8949c0c4
2 changed files with 41 additions and 6 deletions
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23
src/soc/intel/tigerlake/chip.h
View File

@ -133,6 +133,23 @@ struct soc_intel_tigerlake_config {
uint8_t SataPortsEnable[8];
uint8_t SataPortsDevSlp[8];
/*
* Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
* Default 0. Setting this to 1 disables the SATA Power Optimizer.
*/
uint8_t SataPwrOptimizeDisable;
/*
* SATA Port Enable Dito Config.
* Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
*/
uint8_t SataPortsEnableDitoConfig[8];
/* SataPortsDmVal is the DITO multiplier. Default is 15. */
uint8_t SataPortsDmVal[8];
/* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
uint16_t SataPortsDitoVal[8];
/* Audio related */
uint8_t PchHdaDspEnable;
uint8_t PchHdaAudioLinkHdaEnable;
@ -337,12 +354,6 @@ struct soc_intel_tigerlake_config {
*/
uint8_t DmiPwrOptimizeDisable;
/*
* Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
* Default 0. Setting this to 1 disables the SATA Power Optimizer.
*/
uint8_t SataPwrOptimizeDisable;
/* structure containing various settings for PCH FIVRs */
struct {
bool configure_ext_fivr;

24
src/soc/intel/tigerlake/fsp_params.c
View File

@ -24,6 +24,10 @@
#define THC_0 1
#define THC_1 2
/* SATA DEVSLP idle timeout default values */
#define DEF_DMVAL 15
#define DEF_DITOVAL 625
/*
* Chip config parameter PcieRpL1Substates uses (UPD value + 1)
* because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
@ -212,6 +216,26 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable);
params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
/*
* Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
* SataPortsDmVal is the DITO multiplier. Default is 15.
* SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms.
* The default values can be changed from devicetree.
*/
for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) {
if (config->SataPortsEnableDitoConfig[i]) {
if (config->SataPortsDmVal[i])
params->SataPortsDmVal[i] = config->SataPortsDmVal[i];
else
params->SataPortsDmVal[i] = DEF_DMVAL;
if (config->SataPortsDitoVal[i])
params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i];
else
params->SataPortsDitoVal[i] = DEF_DITOVAL;
}
}
/* Enable TCPU for processor thermal control */
params->Device4Enable = config->Device4Enable;