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southbridge/sis/sis966: transition away from device_t 

Replace the use of the old device_t definition inside
southbridge/sis/sis966.

Change-Id: I9e731fedc6f21eaa2685f794ea2172eb4800628b
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16488
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Antonello Dettori 2016-09-03 10:45:33 +02:00 committed by Martin Roth
parent 8126daf6f3
commit 1a9da7acf6
3 changed files with 12 additions and 8 deletions
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2
src/southbridge/sis/sis966/early_ctrl.c
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@ -19,7 +19,7 @@
static unsigned get_sbdn(unsigned bus) static unsigned get_sbdn(unsigned bus)
{ {
device_t dev; pci_devfn_t dev;
/* Find the device. */ /* Find the device. */
dev = pci_locate_device_on_bus( dev = pci_locate_device_on_bus(

16
src/southbridge/sis/sis966/early_smbus.c
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@ -510,10 +510,12 @@ static const uint8_t SiS_SiS1183_init[44][3]={
*/ */
static void Init_Share_Memory(uint8_t ShareSize) static void Init_Share_Memory(uint8_t ShareSize)
{ {
device_t dev; pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS,
pci_write_config8(dev, 0x4C, (pci_read_config8(dev, 0x4C) & 0x1F) | (ShareSize << 5)); PCI_DEVICE_ID_SIS_SIS761), 0);
pci_write_config8(dev, 0x4C, (pci_read_config8(dev, 0x4C) & 0x1F) |
(ShareSize << 5));
} }
/* In: => Aperture size /* In: => Aperture size
@ -526,7 +528,7 @@ static void Init_Share_Memory(uint8_t ShareSize)
*/ */
static void Init_Aper_Size(uint8_t AperSize) static void Init_Aper_Size(uint8_t AperSize)
{ {
device_t dev; pci_devfn_t dev;
uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00}; uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0); dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
@ -538,7 +540,7 @@ static void Init_Aper_Size(uint8_t AperSize)
static void sis_init_stage1(void) static void sis_init_stage1(void)
{ {
device_t dev; pci_devfn_t dev;
uint8_t temp8; uint8_t temp8;
int i; int i;
uint8_t GUI_En; uint8_t GUI_En;
@ -600,7 +602,7 @@ static void sis_init_stage1(void)
static void sis_init_stage2(void) static void sis_init_stage2(void)
{ {
device_t dev; pci_devfn_t dev;
msr_t msr; msr_t msr;
int i; int i;
uint8_t temp8; uint8_t temp8;
@ -711,7 +713,7 @@ static void sis_init_stage2(void)
static void enable_smbus(void) static void enable_smbus(void)
{ {
device_t dev; pci_devfn_t dev;
uint8_t temp8; uint8_t temp8;
printk(BIOS_DEBUG, "enable_smbus -------->\n"); printk(BIOS_DEBUG, "enable_smbus -------->\n");

2
src/southbridge/sis/sis966/sis966.h
View File

@ -31,6 +31,8 @@
#define DEBUG_USB 0 #define DEBUG_USB 0
#define DEBUG_USB2 0 #define DEBUG_USB2 0
#ifndef __SIMPLE_DEVICE__
void sis966_enable(device_t dev); void sis966_enable(device_t dev);
#endif
#endif /* SIS966_H */ #endif /* SIS966_H */