diff --git a/src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg b/src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg index 911e4ae16e..fc7d1a43fb 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg +++ b/src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg @@ -29,7 +29,7 @@ DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin # BDT -PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin L2 -PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin L2 -PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin L2 -PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin L2 +PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin L2 +PSP_PMUD_FILE_SUB0_INS1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin L2 +PSP_PMUI_FILE_SUB0_INS4 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin L2 +PSP_PMUD_FILE_SUB0_INS4 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin L2 diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg index 9757d7249e..ad253982ea 100644 --- a/src/soc/amd/cezanne/fw.cfg +++ b/src/soc/amd/cezanne/fw.cfg @@ -33,8 +33,8 @@ DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin # BDT -PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin -PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin -PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin -PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin +PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin +PSP_PMUD_FILE_SUB0_INS1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin +PSP_PMUI_FILE_SUB0_INS4 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin +PSP_PMUD_FILE_SUB0_INS4 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin PSP_MP2CFG_FILE MP2FWConfig.sbin diff --git a/src/soc/amd/picasso/fw.cfg b/src/soc/amd/picasso/fw.cfg index 516af7bf3a..c9db4b6d59 100644 --- a/src/soc/amd/picasso/fw.cfg +++ b/src/soc/amd/picasso/fw.cfg @@ -29,11 +29,11 @@ PSP_MP2FW2_FILE MP2I2CFWPCO.sbin PSP_MP2CFG_FILE MP2FWConfig.sbin PSP_DRIVERS_FILE drv_sys_prod_RV.sbin # BDT -PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin -PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin -PSP_PMUI_FILE3 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin -PSP_PMUI_FILE4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin -PSP_PMUD_FILE1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin -PSP_PMUD_FILE2 Appb_Rv_2D_Ddr4_Dmem.csbin -PSP_PMUD_FILE3 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin -PSP_PMUD_FILE4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin +PSP_PMUI_FILE_SUB0_INS1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE_SUB0_INS4 Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE_SUB1_INS1 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE_SUB1_INS4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE_SUB0_INS1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE_SUB0_INS4 Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE_SUB1_INS1 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE_SUB1_INS4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin diff --git a/src/soc/amd/sabrina/fw.cfg b/src/soc/amd/sabrina/fw.cfg index 95dd4e138f..f321435c1b 100644 --- a/src/soc/amd/sabrina/fw.cfg +++ b/src/soc/amd/sabrina/fw.cfg @@ -35,8 +35,8 @@ DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin # BDT -PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin -PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin -PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin -PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin +PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin +PSP_PMUD_FILE_SUB0_INS1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin +PSP_PMUI_FILE_SUB0_INS4 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin +PSP_PMUD_FILE_SUB0_INS4 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin PSP_MP2CFG_FILE MP2FWConfig.sbin diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 106ea65b69..d27b7bb1e6 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -331,6 +331,11 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, else return 1; } +#define PMUI_STR_BASE "PSP_PMUI_FILE" +#define PMUD_STR_BASE "PSP_PMUD_FILE" +#define PMU_STR_BASE_LEN strlen(PMUI_STR_BASE) +#define PMU_STR_SUB_INDEX strlen(PMUI_STR_BASE"_SUB") +#define PMU_STR_INS_INDEX strlen(PMUI_STR_BASE"_SUBx_INS") static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename, char level_to_set, amd_cb_config *cb_config) @@ -342,38 +347,14 @@ static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename, (void) (cb_config); /* Remove warning and reserved for future. */ - if (strcmp(fw_name, "PSP_PMUI_FILE1") == 0) { + if (strncmp(fw_name, PMUI_STR_BASE, PMU_STR_BASE_LEN) == 0) { fw_type = AMD_BIOS_PMUI; - subprog = 0; - instance = 1; - } else if (strcmp(fw_name, "PSP_PMUI_FILE2") == 0) { - fw_type = AMD_BIOS_PMUI; - subprog = 0; - instance = 4; - } else if (strcmp(fw_name, "PSP_PMUI_FILE3") == 0) { - fw_type = AMD_BIOS_PMUI; - subprog = 1; - instance = 1; - } else if (strcmp(fw_name, "PSP_PMUI_FILE4") == 0) { - fw_type = AMD_BIOS_PMUI; - subprog = 1; - instance = 4; - } else if (strcmp(fw_name, "PSP_PMUD_FILE1") == 0) { + subprog = fw_name[PMU_STR_SUB_INDEX] - '0'; + instance = fw_name[PMU_STR_INS_INDEX] - '0'; + } else if (strncmp(fw_name, PMUD_STR_BASE, PMU_STR_BASE_LEN) == 0) { fw_type = AMD_BIOS_PMUD; - subprog = 0; - instance = 1; - } else if (strcmp(fw_name, "PSP_PMUD_FILE2") == 0) { - fw_type = AMD_BIOS_PMUD; - subprog = 0; - instance = 4; - } else if (strcmp(fw_name, "PSP_PMUD_FILE3") == 0) { - fw_type = AMD_BIOS_PMUD; - subprog = 1; - instance = 1; - } else if (strcmp(fw_name, "PSP_PMUD_FILE4") == 0) { - fw_type = AMD_BIOS_PMUD; - subprog = 1; - instance = 4; + subprog = fw_name[PMU_STR_SUB_INDEX] - '0'; + instance = fw_name[PMU_STR_INS_INDEX] - '0'; } else if (strcmp(fw_name, "RTM_PUBKEY_FILE") == 0) { fw_type = AMD_BIOS_RTM_PUBKEY; subprog = 0;