soc/amd/picasso/acpi: Remove old AOAC register definitions
We no longer need this code. It's been added differently in CB:42473. BUG=b:153001807, b:154756391 TEST=Build Trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6fe1e465f137ba6afbf9f0dbce501b5fc845e210 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Raul E Rangel
Patrick Georgi
parent
e62a17b118
commit
1aa5cff709
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@ -144,364 +144,3 @@ Method(OSFL, 0){
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}
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Return(OSVR)
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}
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OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000)
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Field( SMIC, ByteAcc, NoLock, Preserve) {
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/* MISC registers */
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offset (0x03ee),
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U3PS, 2, /* Usb3PowerSel */
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offset (0x0e28),
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,29 ,
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SARP, 1, /* Sata Ref Clock Powerdown */
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U2RP, 1, /* Usb2 Ref Clock Powerdown */
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U3RP, 1, /* Usb3 Ref Clock Powerdown */
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/* AOAC Registers */
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offset (0x1e4a), /* I2C0 D3 Control */
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I0TD, 2,
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, 1,
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I0PD, 1,
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offset (0x1e4b), /* I2C0 D3 State */
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I0DS, 3,
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offset (0x1e4c), /* I2C1 D3 Control */
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I1TD, 2,
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, 1,
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I1PD, 1,
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offset (0x1e4d), /* I2C1 D3 State */
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I1DS, 3,
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offset (0x1e4e), /* I2C2 D3 Control */
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I2TD, 2,
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, 1,
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I2PD, 1,
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offset (0x1e4f), /* I2C2 D3 State */
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I2DS, 3,
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offset (0x1e50), /* I2C3 D3 Control */
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I3TD, 2,
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, 1,
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I3PD, 1,
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offset (0x1e51), /* I2C3 D3 State */
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I3DS, 3,
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offset (0x1e56), /* UART0 D3 Control */
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U0TD, 2,
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, 1,
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U0PD, 1,
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offset (0x1e57), /* UART0 D3 State */
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U0DS, 3,
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offset (0x1e58), /* UART1 D3 Control */
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U1TD, 2,
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, 1,
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U1PD, 1,
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offset (0x1e59), /* UART1 D3 State */
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U1DS, 3,
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offset (0x1e60), /* UART2 D3 Control */
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U2TD, 2,
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, 1,
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U2PD, 1,
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offset (0x1e61), /* UART2 D3 State */
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U2DS, 3,
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offset (0x1e71), /* SD D3 State */
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SDDS, 3,
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offset (0x1e74), /* UART3 D3 Control */
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U3TD, 2,
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, 1,
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U3PD, 1,
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offset (0x1e75), /* UART3 D3 State */
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U3DS, 3,
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offset (0x1e80), /* Shadow Register Request */
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, 15,
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RQ15, 1,
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, 2,
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RQ18, 1,
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, 4,
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RQ23, 1,
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RQ24, 1,
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, 5,
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RQTY, 1,
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offset (0x1e84), /* Shadow Register Status */
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, 15,
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SASR, 1, /* SATA 15 Shadow Reg Request Status Register */
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, 2,
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U2SR, 1, /* USB2 18 Shadow Reg Request Status Register */
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, 4,
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U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */
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SDSR, 1, /* SD 24 Shadow Reg Request Status Register */
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offset (0x1ea0), /* PwrGood Control */
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PG1A, 1,
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PG2_, 1,
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,1,
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U3PG, 1, /* Usb3 Power Good BIT3 */
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offset (0x1ea3), /* PwrGood Control b[31:24] */
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PGA3, 8 ,
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}
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OperationRegion(FCFG, SystemMemory, PCBA, 0x01000000)
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Field(FCFG, DwordAcc, NoLock, Preserve)
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{
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/* XHCI */
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Offset(0x00080010), /* Base address */
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XHBA, 32,
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Offset(0x0008002c), /* Subsystem ID / Vendor ID */
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XH2C, 32,
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Offset(0x00080048), /* Indirect PCI Index Register */
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IDEX, 32,
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DATA, 32,
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Offset(0x00080054), /* PME Control / Status */
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U_PS, 2,
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/* EHCI */
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Offset(0x00090004), /* Control */
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, 1,
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EHME, 1,
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Offset(0x00090010), /* Base address */
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EHBA, 32,
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Offset(0x0009002c), /* Subsystem ID / Vendor ID */
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EH2C, 32,
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Offset(0x00090054), /* EHCI Spare 1 */
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EH54, 8,
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Offset(0x00090064), /* Misc Control 2 */
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EH64, 8,
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Offset(0x000900c4), /* PME Control / Status */
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E_PS, 2,
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/* LPC Bridge */
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Offset(0x000a30cb), /* ClientRomProtect[31:24] */
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, 7,
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AUSS, 1, /* AutoSizeStart */
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}
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/*
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* Arg0:device:
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* 5=I2C0, 6=I2C1, 7=I2C2, 8=I2C3, 11=UART0, 12=UART1,
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* 18=EHCI, 23=xHCI, 24=SD
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* Arg1:D-state
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*/
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Mutex (FDAS, 0) /* FCH Device AOAC Semophore */
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Method(FDDC, 2, Serialized)
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{
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Acquire(FDAS, 0xffff)
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if(LEqual(Arg1, 0)) {
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Switch(ToInteger(Arg0)) {
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Case(Package() {5, 15, 24}) {
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Store(One, PG1A)
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}
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Case(Package() {6, 7, 8, 11, 12, 18}) {
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Store(One, PG2_)
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}
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}
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/* put device into D0 */
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Switch(ToInteger(Arg0))
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{
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Case(5) {
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Store(0x00, I0TD)
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Store(One, I0PD)
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Store(I0DS, Local0)
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while(LNotEqual(Local0,0x7)) {
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Store(I0DS, Local0)
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}
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}
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Case(6) {
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Store(0x00, I1TD)
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Store(One, I1PD)
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Store(I1DS, Local0)
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while(LNotEqual(Local0,0x7)) {
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Store(I1DS, Local0)
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}
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}
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Case(7) {
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Store(0x00, I2TD)
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Store(One, I2PD)
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Store(I2DS, Local0)
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while(LNotEqual(Local0,0x7)) {
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Store(I2DS, Local0)
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}
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}
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Case(8) {Store(0x00, I3TD)
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Store(One, I3PD)
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Store(I3DS, Local0)
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while(LNotEqual(Local0,0x7)) {
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Store(I3DS, Local0)
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}
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}
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Case(11) {
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Store(0x00, U0TD)
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Store(One, U0PD)
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Store(U0DS, Local0)
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while(LNotEqual(Local0,0x7)) {
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Store(U0DS, Local0)
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}
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}
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Case(12) {
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Store(0x00, U1TD)
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Store(One, U1PD)
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Store(U1DS, Local0)
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while(LNotEqual(Local0,0x7)) {
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Store(U1DS, Local0)
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}
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}
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Case(16) {
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Store(0x00, U2TD)
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Store(One, U2PD)
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Store(U2DS, Local0)
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while(LNotEqual(Local0,0x7)) {
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Store(U2DS, Local0)
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}
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}
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Case(26) {
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Store(0x00, U3TD)
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Store(One, U3PD)
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Store(U3DS, Local0)
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while(LNotEqual(Local0,0x7)) {
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Store(U3DS, Local0)
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}
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}
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}
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} else {
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/* put device into D3cold */
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Switch(ToInteger(Arg0))
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{
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Case(5) {
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Store(Zero, I0PD)
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Store(I0DS, Local0)
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while(LNotEqual(Local0,0x0)) {
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Store(I0DS, Local0)
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}
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Store(0x03, I0TD)
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}
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Case(6) {
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Store(Zero, I1PD)
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Store(I1DS, Local0)
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while(LNotEqual(Local0,0x0)) {
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Store(I1DS, Local0)
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}
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Store(0x03, I1TD)
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}
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Case(7) {
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Store(Zero, I2PD)
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Store(I2DS, Local0)
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while(LNotEqual(Local0,0x0)) {
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Store(I2DS, Local0)
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}
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Store(0x03, I2TD)}
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Case(8) {
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Store(Zero, I3PD)
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Store(I3DS, Local0)
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while(LNotEqual(Local0,0x0)) {
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Store(I3DS, Local0)
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}
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Store(0x03, I3TD)
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}
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Case(11) {
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Store(Zero, U0PD)
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Store(U0DS, Local0)
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while(LNotEqual(Local0,0x0)) {
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Store(U0DS, Local0)
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}
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Store(0x03, U0TD)
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}
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Case(12) {
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Store(Zero, U1PD)
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Store(U1DS, Local0)
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while(LNotEqual(Local0,0x0)) {
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Store(U1DS, Local0)
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}
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Store(0x03, U1TD)
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}
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Case(16) {
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Store(Zero, U2PD)
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Store(U2DS, Local0)
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while(LNotEqual(Local0,0x0)) {
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Store(U2DS, Local0)
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}
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Store(0x03, U2TD)
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}
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Case(26) {
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Store(Zero, U3PD)
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Store(U3DS, Local0)
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while(LNotEqual(Local0,0x0)) {
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Store(U3DS, Local0)
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}
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Store(0x03, U3TD)
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}
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}
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if(LEqual(I1TD, 3)) {
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if(LEqual(I2TD, 3)) {
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if(LEqual(I3TD, 3)) {
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if(LEqual(U0TD, 3)) {
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if(LEqual(U1TD, 3)) {
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Store(Zero, PG2_)
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}
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}
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}
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}
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}
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}
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Release(FDAS)
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}
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Method(FPTS,0, Serialized) /* FCH _PTS */
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{
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}
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Method(FWAK,0, Serialized) /* FCH _WAK */
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{
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if(LEqual(\UT0E, zero)) {
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if(LNotEqual(U0TD, 0x03)) {
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FDDC(11, 3)
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}
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}
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if(LEqual(\UT1E, zero)) {
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if(LNotEqual(U1TD, 0x03)) {
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FDDC(12, 3)
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}
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}
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if(LEqual(\IC2E, zero)) {
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if(LNotEqual(I2TD, 0x03)) {
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FDDC(7, 3)
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}
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}
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if(LEqual(\IC3E, zero)) {
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if(LNotEqual(I3TD, 0x03)) {
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FDDC(8, 3)
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}
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}
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}
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/*
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* Helper for setting a bit in AOACxA0 PwrGood Control
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* Arg0: bit to set or clear
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* Arg1: 0 = clear bit[Arg0], non-zero = set bit[Arg0]
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*/
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Method(PWGC,2, Serialized)
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{
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And (PGA3, 0xdf, Local0) /* do SwUsb3SlpShutdown below */
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if(Arg1) {
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Or(Arg0, Local0, Local0)
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} else {
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Not(Arg0, Local1)
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And(Local1, Local0, Local0)
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}
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Store(Local0, PGA3)
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if(LEqual(Arg0, 0x20)) { /* if SwUsb3SlpShutdown */
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Store(PGA3, Local0)
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And(Arg0, Local0, Local0)
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while(LNot(Local0)) { /* wait SwUsb3SlpShutdown to complete */
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Store(PGA3, Local0)
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And(Arg0, Local0, Local0)
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}
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}
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}
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