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soc/intel/tigerlake: Configure TCSS xHCI and xDCI 

Configure xHCI, xDCI according to board design

BUG=none
BRANCH=none
TEST=Build and boot to OS

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Wonkyu Kim 2020-01-28 22:06:37 -08:00 committed by Patrick Georgi
parent e7601b5d6c
commit 1ab6f0c176
2 changed files with 10 additions and 2 deletions
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6
src/soc/intel/tigerlake/chip.h
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Intel Corporation.
* Copyright (C) 2019-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -218,6 +218,10 @@ struct soc_intel_tigerlake_config {
FORCE_ENABLE,
} CnviBtAudioOffload;
/* Tcss */
uint8_t TcssXhciEn;
uint8_t TcssXdciEn;
/*
* Override GPIO PM configuration:
* 0: Use FSP default GPIO PM program,

6
src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Intel Corp.
* Copyright (C) 2019-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -105,6 +105,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* Image clock: disable all clocks for bypassing FSP pin mux */
memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
/* Tcss */
m_cfg->TcssXhciEn = config->TcssXhciEn;
m_cfg->TcssXdciEn = config->TcssXdciEn;
/* Enable Hyper Threading */
m_cfg->HyperThreading = 1;
/* Disable Lock PCU Thermal Management registers */