gru: Fix and export SPK_PA_EN GPIO for Scarlet

On older Grus, GPIO0_A2 was an audio voltage rail enable line. On
Scarlet, we instead moved the audio codec enable (previously on
GPIO1_A2) there. Unfortunately the code still had some hardcoded
leftovers that were overlooked in the initial port and make our speakers
smell weird.

This patch fixes the incorrect GPIO settings and adds the speaker enable
pin to the GPIOs passed through the coreboot table, so that depthcharge
doesn't have to keep its own definition of the pin which may go out of
sync.

Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Julius Werner 2017-11-03 15:23:09 -07:00
parent 59e9080dcb
commit 1ab8c01050
3 changed files with 6 additions and 5 deletions

View File

@ -31,6 +31,7 @@
#define GPIO_P15V_EN dead_code_t(gpio_t, "PP1500 doesn't exist on Scarlet")
#define GPIO_P18V_AUDIO_PWREN dead_code_t(gpio_t, "doesn't exist on Scarlet")
#define GPIO_P30V_EN GPIO(0, B, 1)
#define GPIO_SPK_PA_EN GPIO(0, A, 2)
#define GPIO_TP_RST_L dead_code_t(gpio_t, "don't need TP_RST_L on Scarlet")
#define GPIO_TPM_IRQ GPIO(1, C, 1)
#define GPIO_WP GPIO(0, B, 5)
@ -41,6 +42,7 @@
#define GPIO_P15V_EN GPIO(0, B, 2)
#define GPIO_P18V_AUDIO_PWREN GPIO(0, A, 2)
#define GPIO_P30V_EN GPIO(0, B, 4)
#define GPIO_SPK_PA_EN GPIO(1, A, 2)
#define GPIO_TP_RST_L GPIO(3, B, 4) /* may also be an I2C pull-up enable */
#define GPIO_TPM_IRQ GPIO(0, A, 5)
#define GPIO_WP GPIO(1, C, 2)

View File

@ -36,6 +36,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"},
{GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"},
{GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"},
{GPIO_SPK_PA_EN.raw, ACTIVE_HIGH, -1, "speaker enable"},
#if IS_ENABLED(CONFIG_GRU_HAS_TPM2)
{GPIO_TPM_IRQ.raw, ACTIVE_HIGH, -1, "TPM interrupt"},
#endif

View File

@ -226,11 +226,9 @@ static void configure_codec(void)
/* AUDIO IO domain 1.8V voltage selection */
write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1));
/* CPU1_P1.8V_AUDIO_PWREN for P1.8_AUDIO */
gpio_output(GPIO(0, A, 2), 1);
/* set CPU1_SPK_PA_EN output */
gpio_output(GPIO(1, A, 2), 0);
if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET))
gpio_output(GPIO_P18V_AUDIO_PWREN, 1);
gpio_output(GPIO_SPK_PA_EN, 0);
rkclk_configure_i2s(12288000);
}