soc/intel/cannonlake: Define VR settings
Define VR settings configuration as per board design. BUG=N/A TEST=Build and boot up into sarien platform. Change-Id: Ic9927943b1f8fab687659fd1d6da0e3988a3aba2 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/31405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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@ -55,6 +55,8 @@ struct vr_config {
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uint16_t dc_loadline;
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};
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#define VR_CFG_AMP(i) ((i) * 4)
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/* VrConfig Settings for 4 domains
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* 0 = System Agent, 1 = IA Core,
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* 2 = GT unsliced, 3 = GT sliced */
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@ -19,7 +19,54 @@
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#include <soc/vr_config.h>
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static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
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/* TODO: define this*/
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[VR_SYSTEM_AGENT] = {
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(6),
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.voltage_limit = 1520,
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},
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[VR_IA_CORE] = {
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(70),
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.voltage_limit = 1520,
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},
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[VR_GT_UNSLICED] = {
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(31),
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.voltage_limit = 1520,
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},
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[VR_GT_SLICED] = {
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(31),
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.voltage_limit = 1520,
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},
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};
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void fill_vr_domain_config(void *params,
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