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mainboard/google/reef: Configure PERST pin for reef DVT 

Configure GPIO 122 as PERST on DVT. This is to assert WiFi PERST
during s0ix entry.


BUG=chrome-os-partner:55877
TEST=S0ix functional on DVT

Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>

Change-Id: Iab18b2de621a1a9226c78493f6defa15081db875
Reviewed-on: https://review.coreboot.org/17030
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Vaibhav Shankar 2016-10-14 16:08:32 -07:00 committed by Aaron Durbin
parent 58caa8ba8c
commit 1ac773fa55
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/reef/variants/baseboard/devicetree.cb
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@ -15,7 +15,7 @@ chip soc/intel/apollolake
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
register "prt0_gpio" = "GPIO_PRT0_UDEF"
register "prt0_gpio" = "GPIO_122"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.