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mb/amd/chausie/devicetree: add PCIe clock output configuration 

The general purpose PCIe clock outputs 0, 1 and 3 are used with their
corresponding clock request pins, so set the gpp_clk_config to
GPP_CLK_REQ for those and disable the unused output 2. This matches the
DXIO descriptor in port_descriptors.c.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38ab8d6d824617509fdd18f06d5593889ec50666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65112
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-06-13 17:19:04 +02:00
parent 68305aa3b0
commit 1acb133e2d
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/amd/chausie/devicetree.cb
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@ -149,6 +149,11 @@ chip soc/amd/sabrina
.PhyP3CpmP4Support = 0, .PhyP3CpmP4Support = 0,
}" }"
register "gpp_clk_config[0]" = "GPP_CLK_REQ"
register "gpp_clk_config[1]" = "GPP_CLK_REQ"
register "gpp_clk_config[2]" = "GPP_CLK_OFF"
register "gpp_clk_config[3]" = "GPP_CLK_REQ"
device domain 0 on device domain 0 on
device ref iommu on end device ref iommu on end
device ref gpp_bridge_0 on end # GBE device ref gpp_bridge_0 on end # GBE