GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/brya/primus: add NVMe power and reset pin to early_gpio_table 

NVMe needs extra time to run boot process, enable power and deassert
reset for NVMe earlier in the boot flow that primus can successfully
boot into OS with non-serial coreboot.

BUG=b:199967106
TEST=USE="project_primus" emerge-brya coreboot and verify it builds
without error.

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I9c66efe96515347502d059556052c764c1be5d09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Malik_Hsu 2021-09-15 13:22:23 +08:00 committed by Felix Held
parent 8d46db20a3
commit 1ad9ff8156
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/mainboard/google/brya/variants/primus/gpio.c
View File

@ -94,6 +94,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_D1, 0, DEEP), PAD_CFG_GPO(GPP_D1, 0, DEEP),
/* D2 : ISH_GP2 ==> EN_FP_PWR */ /* D2 : ISH_GP2 ==> EN_FP_PWR */
PAD_CFG_GPO(GPP_D2, 1, DEEP), PAD_CFG_GPO(GPP_D2, 1, DEEP),
/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_D11, 1, DEEP),
/* D18 : UART1_TXD ==> SD_PE_RST_L */ /* D18 : UART1_TXD ==> SD_PE_RST_L */
PAD_CFG_GPO(GPP_D18, 0, PLTRST), PAD_CFG_GPO(GPP_D18, 0, PLTRST),
/* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */
@ -110,6 +112,11 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* H13 : I2C7_SCL ==> EN_PP3300_SD */ /* H13 : I2C7_SCL ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_H13, 1, PLTRST), PAD_CFG_GPO(GPP_H13, 1, PLTRST),
/* B4 : PROC_GP3 ==> SSD_PERST_L
* SSD_PERST_L is released after EN_PP3300_SSD is asserted; the
* power rails take some time to come up.
*/
PAD_CFG_GPO(GPP_B4, 1, DEEP),
}; };
const struct pad_config *variant_gpio_override_table(size_t *num) const struct pad_config *variant_gpio_override_table(size_t *num)