sb/intel/common: Add common detect_s3_resume

Add a common detect_s3_resume function.
Will be used by other southbridge code.

TODO: Merge with soc/intel/common/*/pmclib

Tested on Lenovo T520 (Intel Sandy Bridge) with Change
I283a841575430f2f179997db8d2f08fa3978a0bb applied as well.
Still boots to OS, no errors visible in dmesg and S3 resume is working.

Change-Id: I88023af522afac8164f068b0fbe0eac601aef702
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/southbridge/intel/common/Kconfig

@@ -6,6 +6,10 @@ config SOUTHBRIDGE_INTEL_COMMON_RESET
 	bool
 	select HAVE_CF9_RESET
 
+config SOUTHBRIDGE_INTEL_COMMON_PMCLIB
+	def_bool n
+	depends on SOUTHBRIDGE_INTEL_COMMON
+
 config SOUTHBRIDGE_INTEL_COMMON_GPIO
 	def_bool n
 

src/southbridge/intel/common/Makefile.inc

@@ -25,6 +25,8 @@ postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
 romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
 ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
 
+romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c
+
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
 
 romstage-y += pmbase.c

src/southbridge/intel/common/pmclib.c

@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+
+#include "pmclib.h"
+#include "pmbase.h"
+#include "pmutil.h"
+
+int southbridge_detect_s3_resume(void)
+{
+	u32 pm1_cnt;
+	u16 pm1_sts;
+	int is_s3 = 0;
+
+	/* Check PM1_STS[15] to see if we are waking from Sx */
+	pm1_sts = read_pmbase16(PM1_STS);
+	if (pm1_sts & WAK_STS) {
+		/* Read PM1_CNT[12:10] to determine which Sx state */
+		pm1_cnt = read_pmbase32(PM1_CNT);
+		if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) {
+			/* Clear SLP_TYPE. */
+			write_pmbase32(PM1_CNT, pm1_cnt & ~(7 << 10));
+			is_s3 = 1;
+		}
+	}
+	if (is_s3) {
+		if (!acpi_s3_resume_allowed()) {
+			printk(BIOS_DEBUG, "SB: Resume from S3 detected, but disabled.\n");
+			return 0;
+		}
+
+		printk(BIOS_DEBUG, "SB: Resume from S3 detected.\n");
+	}
+
+	return is_s3;
+}

src/southbridge/intel/common/pmclib.h

@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef INTEL_COMMON_PMCLIB_H
+#define INTEL_COMMON_PMCLIB_H
+
+/*
+ * Returns 1 if platform was in ACPI S3 power state and CONFIG(ACPI_RESUME)
+ * is enabled else returns 0.
+ */
+int southbridge_detect_s3_resume(void);
+
+#endif