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mb/siemens/mc_ehl4: Enable PCIe devices 

Correct the remaining PCI devices, differing from the ehl1 mainboard.

Change-Id: Ie09188b72a62c4d5cba2fcda6f60f3bc0098633e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit is contained in:
Mario Scheithauer 2023-03-17 09:56:55 +01:00 committed by Lean Sheng Tan
parent 4f37cf0735
commit 1af4b289f0
1 changed files with 7 additions and 7 deletions
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14
src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
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@ -44,14 +44,14 @@ chip soc/intel/elkhartlake
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"
register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
@ -65,14 +65,14 @@ chip soc/intel/elkhartlake
register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
# Disable LTR for all PCIe root ports
register "PcieRpLtrDisable[0]" = "true"
register "PcieRpLtrDisable[1]" = "true"
register "PcieRpLtrDisable[2]" = "true"
register "PcieRpLtrDisable[3]" = "true"
register "PcieRpLtrDisable[6]" = "true"
register "PcieRpLtrDisable[4]" = "true"
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
@ -159,7 +159,7 @@ chip soc/intel/elkhartlake
device pci 1c.1 on end # RP2 (pcie0 single VC)
device pci 1c.2 on end # RP3 (pcie0 single VC)
device pci 1c.3 on end # RP4 (pcie0 single VC)
device pci 1c.6 on end # RP7 (pcie3 multi VC)
device pci 1c.4 on end # RP5 (pcie1 multi VC)
device pci 1e.0 on end # UART0
device pci 1e.1 on end # UART1