From 1af7b5ddf116ac1cb3c7acf5a116b60f7a942f4a Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 21 Aug 2014 12:52:06 -0700 Subject: [PATCH] arm64: Initialize exception stack Initialize the exception stack on stage_entry BUG=chrome-os-partner:31515 BRANCH=None TEST=Exception handling works fine Change-Id: I66b4e73e77ad746e891cb2ae6662fbf0531f9d8a Signed-off-by: Patrick Georgi Original-Commit-Id: a21d0a432e1742fd8b36b3f8fc7748152f7d74d2 Original-Change-Id: I0b6fb95c660c68fb47a30e905acb910b0e2eafea Original-Signed-off-by: Furquan Shaikh Original-Reviewed-on: https://chromium-review.googlesource.com/213673 Original-Tested-by: Furquan Shaikh Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Furquan Shaikh Reviewed-on: http://review.coreboot.org/8999 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/arm64/stage_entry.S | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index c18c9cfeaa..4c26f65707 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -55,6 +55,16 @@ ENTRY(arm64_el3_startup) and x0, x0, x1 msr SCR_EL3, x0 + /* Initialize SP_EL3 as exception stack */ + ldr x0, .exception_stack_top + cmp x0, #0 + b.eq 2f + msr SPSel, #1 + isb + + mov sp, x0 + + 2: /* Have stack pointer use SP_EL0. */ msr SPSel, #0 isb @@ -81,6 +91,8 @@ ENTRY(arm64_el3_startup) * to the Kconfig option for cpu0. However, this code can be relocated * and reused to start up secondary cpus. */ + .exception_stack_top: + .quad CONFIG_EXCEPTION_STACK_TOP .stack_top: .quad _estack .entry: