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nyans: reduce code duplication in bootblock and romstages 

this change reduces the code duplication of the bootblock and the romstages for
Nyans.

BUG=none
TEST=Built Nyan, Big, and Blaze. Ran faft on Blaze.
BRANCH=none
Original-Signed-off-by: dnojiri@chromium.org (Daisuke Nojiri)
Original-Change-Id: Ieb9dac3b061a2cf46c63afb2f31eb67ab391ea1a
Original-Reviewed-on: https://chromium-review.googlesource.com/214050
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>

(cherry picked from commit f3413d39458f03895fe4963a41285f71d81bcf5f)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I912f63b12321aa26a7add302fc8a6c4e607330ef
Reviewed-on: http://review.coreboot.org/8880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Daisuke Nojiri 2014-08-27 11:48:03 -07:00 committed by Aaron Durbin
parent dad16b1c58
commit 1b05d887d7
16 changed files with 460 additions and 479 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/nyan/Makefile.inc
View File

@ -36,6 +36,7 @@ romstage-y += reset.c
romstage-y += romstage.c romstage-y += romstage.c
romstage-y += sdram_configs.c romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += early_configs.c
ramstage-y += boardid.c ramstage-y += boardid.c
ramstage-y += mainboard.c ramstage-y += mainboard.c

103
src/mainboard/google/nyan/early_configs.c Normal file
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@ -0,0 +1,103 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <soc/nvidia/tegra124/early_configs.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void setup_pinmux(void)
{
/* Write protect. */
gpio_input_pullup(GPIO(R1));
/* Recovery mode. */
gpio_input_pullup(GPIO(Q7));
/* Lid switch. */
gpio_input_pullup(GPIO(R4));
/* Power switch. */
gpio_input_pullup(GPIO(Q0));
/* Developer mode. */
gpio_input_pullup(GPIO(Q6));
/* EC in RW. */
gpio_input_pullup(GPIO(U4));
/* route PU4/5 to GMI to remove conflict w/PWM1/2. */
pinmux_set_config(PINMUX_GPIO_PU4_INDEX,
PINMUX_GPIO_PU4_FUNC_NOR); /* s/b GMI */
pinmux_set_config(PINMUX_GPIO_PU5_INDEX,
PINMUX_GPIO_PU5_FUNC_NOR); /* s/b GMI */
/* SOC and TPM reset GPIO, active low. */
gpio_output(GPIO(I5), 1);
/* SPI1 MOSI */
pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
/* SPI1 MISO */
pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
/* SPI1 SCLK */
pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
/* SPI1 CS0 */
pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
/* I2C3 (cam) clock. */
pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
/* I2C3 (cam) data. */
pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
/* switch unused pin to GPIO */
gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO);
}
static void configure_ec_spi_bus(void)
{
clock_configure_source(sbc1, CLK_M, 3000);
}
static void configure_tpm_i2c_bus(void)
{
clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
i2c_init(2);
}
void early_mainboard_init(void)
{
clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0);
setup_pinmux();
configure_ec_spi_bus();
configure_tpm_i2c_bus();
}

121
src/mainboard/google/nyan/romstage.c
View File

@ -30,8 +30,10 @@
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#include "sdram_configs.h" #include "sdram_configs.h"
#include <soc/nvidia/tegra/i2c.h> #include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/cache.h>
#include <soc/nvidia/tegra124/chip.h> #include <soc/nvidia/tegra124/chip.h>
#include <soc/nvidia/tegra124/clk_rst.h> #include <soc/nvidia/tegra124/clk_rst.h>
#include <soc/nvidia/tegra124/early_configs.h>
#include <soc/nvidia/tegra124/power.h> #include <soc/nvidia/tegra124/power.h>
#include <soc/nvidia/tegra124/sdram.h> #include <soc/nvidia/tegra124/sdram.h>
#include <soc/addressmap.h> #include <soc/addressmap.h>
@ -39,120 +41,12 @@
#include <soc/display.h> #include <soc/display.h>
#include <timestamp.h> #include <timestamp.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
enum {
L2CTLR_ECC_PARITY = 0x1 << 21,
L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6,
L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0,
L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0
};
enum {
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27,
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7,
L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3
};
/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */
static void configure_l2ctlr(void)
{
uint32_t val;
val = read_l2ctlr();
val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK);
val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 |
L2CTLR_ECC_PARITY);
write_l2ctlr(val);
}
/* Configures L2 Auxiliary Control Register for Cortex A15. */
static void configure_l2actlr(void)
{
uint32_t val;
val = read_l2actlr();
val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL |
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT |
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE);
write_l2actlr(val);
}
static void setup_pinmux(void)
{
// Write protect.
gpio_input_pullup(GPIO(R1));
// Recovery mode.
gpio_input_pullup(GPIO(Q7));
// Lid switch.
gpio_input_pullup(GPIO(R4));
// Power switch.
gpio_input_pullup(GPIO(Q0));
// Developer mode.
gpio_input_pullup(GPIO(Q6));
// EC in RW.
gpio_input_pullup(GPIO(U4));
// route PU4/5 to GMI to remove conflict w/PWM1/2.
pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); //s/b GMI
pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); //s/b GMI
// SOC and TPM reset GPIO, active low.
gpio_output(GPIO(I5), 1);
// SPI1 MOSI
pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 MISO
pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 SCLK
pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 CS0
pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// I2C3 (cam) clock.
pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// I2C3 (cam) data.
pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// switch unused pin to GPIO
gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO);
}
static void configure_ec_spi_bus(void)
{
clock_configure_source(sbc1, CLK_M, 3000);
}
static void configure_tpm_i2c_bus(void)
{
clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
i2c_init(2);
}
static void __attribute__((noinline)) romstage(void) static void __attribute__((noinline)) romstage(void)
{ {
timestamp_init(0); timestamp_init(0);
timestamp_add_now(TS_START_ROMSTAGE); timestamp_add_now(TS_START_ROMSTAGE);
configure_l2ctlr(); configure_l2_cache();
configure_l2actlr();
console_init(); console_init();
exception_init(); exception_init();
@ -191,13 +85,10 @@ static void __attribute__((noinline)) romstage(void)
cbmem_initialize_empty(); cbmem_initialize_empty();
// Enable additional peripherals we need for ROM stage. timestamp_init(0);
clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); timestamp_add(TS_START_ROMSTAGE, romstage_start_time);
setup_pinmux(); early_mainboard_init();
configure_ec_spi_bus();
configure_tpm_i2c_bus();
vboot_verify_firmware(romstage_handoff_find_or_add()); vboot_verify_firmware(romstage_handoff_find_or_add());

1
src/mainboard/google/nyan_big/Makefile.inc
View File

@ -35,6 +35,7 @@ romstage-y += reset.c
romstage-y += romstage.c romstage-y += romstage.c
romstage-y += sdram_configs.c romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += early_configs.c
ramstage-y += boardid.c ramstage-y += boardid.c
ramstage-y += mainboard.c ramstage-y += mainboard.c

103
src/mainboard/google/nyan_big/early_configs.c Normal file
View File

@ -0,0 +1,103 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <soc/nvidia/tegra124/early_configs.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void setup_pinmux(void)
{
/* Write protect. */
gpio_input_pullup(GPIO(R1));
/* Recovery mode. */
gpio_input_pullup(GPIO(Q7));
/* Lid switch. */
gpio_input_pullup(GPIO(R4));
/* Power switch. */
gpio_input_pullup(GPIO(Q0));
/* Developer mode. */
gpio_input_pullup(GPIO(Q6));
/* EC in RW. */
gpio_input_pullup(GPIO(U4));
/* route PU4/5 to GMI to remove conflict w/PWM1/2. */
pinmux_set_config(PINMUX_GPIO_PU4_INDEX,
PINMUX_GPIO_PU4_FUNC_NOR); /* s/b GMI */
pinmux_set_config(PINMUX_GPIO_PU5_INDEX,
PINMUX_GPIO_PU5_FUNC_NOR); /* s/b GMI */
/* SOC and TPM reset GPIO, active low. */
gpio_output(GPIO(I5), 1);
/* SPI1 MOSI */
pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
/* SPI1 MISO */
pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
/* SPI1 SCLK */
pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
/* SPI1 CS0 */
pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
/* I2C3 (cam) clock. */
pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
/* I2C3 (cam) data. */
pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
/* switch unused pin to GPIO */
gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO);
}
static void configure_ec_spi_bus(void)
{
clock_configure_source(sbc1, CLK_M, 3000);
}
static void configure_tpm_i2c_bus(void)
{
clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
i2c_init(2);
}
void early_mainboard_init(void)
{
clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0);
setup_pinmux();
configure_ec_spi_bus();
configure_tpm_i2c_bus();
}

121
src/mainboard/google/nyan_big/romstage.c
View File

@ -30,8 +30,10 @@
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#include "sdram_configs.h" #include "sdram_configs.h"
#include <soc/nvidia/tegra/i2c.h> #include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/cache.h>
#include <soc/nvidia/tegra124/chip.h> #include <soc/nvidia/tegra124/chip.h>
#include <soc/nvidia/tegra124/clk_rst.h> #include <soc/nvidia/tegra124/clk_rst.h>
#include <soc/nvidia/tegra124/early_configs.h>
#include <soc/nvidia/tegra124/power.h> #include <soc/nvidia/tegra124/power.h>
#include <soc/nvidia/tegra124/sdram.h> #include <soc/nvidia/tegra124/sdram.h>
#include <soc/addressmap.h> #include <soc/addressmap.h>
@ -39,120 +41,12 @@
#include <soc/display.h> #include <soc/display.h>
#include <timestamp.h> #include <timestamp.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
enum {
L2CTLR_ECC_PARITY = 0x1 << 21,
L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6,
L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0,
L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0
};
enum {
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27,
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7,
L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3
};
/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */
static void configure_l2ctlr(void)
{
uint32_t val;
val = read_l2ctlr();
val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK);
val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 |
L2CTLR_ECC_PARITY);
write_l2ctlr(val);
}
/* Configures L2 Auxiliary Control Register for Cortex A15. */
static void configure_l2actlr(void)
{
uint32_t val;
val = read_l2actlr();
val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL |
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT |
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE);
write_l2actlr(val);
}
static void setup_pinmux(void)
{
// Write protect.
gpio_input_pullup(GPIO(R1));
// Recovery mode.
gpio_input_pullup(GPIO(Q7));
// Lid switch.
gpio_input_pullup(GPIO(R4));
// Power switch.
gpio_input_pullup(GPIO(Q0));
// Developer mode.
gpio_input_pullup(GPIO(Q6));
// EC in RW.
gpio_input_pullup(GPIO(U4));
// route PU4/5 to GMI to remove conflict w/PWM1/2.
pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); //s/b GMI
pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); //s/b GMI
// SOC and TPM reset GPIO, active low.
gpio_output(GPIO(I5), 1);
// SPI1 MOSI
pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 MISO
pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 SCLK
pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 CS0
pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// I2C3 (cam) clock.
pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// I2C3 (cam) data.
pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// switch unused pin to GPIO
gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO);
}
static void configure_ec_spi_bus(void)
{
clock_configure_source(sbc1, CLK_M, 3000);
}
static void configure_tpm_i2c_bus(void)
{
clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
i2c_init(2);
}
static void __attribute__((noinline)) romstage(void) static void __attribute__((noinline)) romstage(void)
{ {
timestamp_init(0); timestamp_init(0);
timestamp_add_now(TS_START_ROMSTAGE); timestamp_add_now(TS_START_ROMSTAGE);
configure_l2ctlr(); configure_l2_cache();
configure_l2actlr();
console_init(); console_init();
exception_init(); exception_init();
@ -191,13 +85,10 @@ static void __attribute__((noinline)) romstage(void)
cbmem_initialize_empty(); cbmem_initialize_empty();
// Enable additional peripherals we need for ROM stage. timestamp_init(0);
clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); timestamp_add(TS_START_ROMSTAGE, romstage_start_time);
setup_pinmux(); early_mainboard_init();
configure_ec_spi_bus();
configure_tpm_i2c_bus();
vboot_verify_firmware(romstage_handoff_find_or_add()); vboot_verify_firmware(romstage_handoff_find_or_add());

2
src/mainboard/google/nyan_blaze/Makefile.inc
View File

@ -30,10 +30,12 @@ subdirs-y += bct
bootblock-y += bootblock.c bootblock-y += bootblock.c
bootblock-y += pmic.c bootblock-y += pmic.c
bootblock-y += reset.c bootblock-y += reset.c
bootblock-y += early_configs.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c
verstage-y += reset.c verstage-y += reset.c
romstage-y += early_configs.c
romstage-y += reset.c romstage-y += reset.c
romstage-y += romstage.c romstage-y += romstage.c
romstage-y += sdram_configs.c romstage-y += sdram_configs.c

103
src/mainboard/google/nyan_blaze/early_configs.c Normal file
View File

@ -0,0 +1,103 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <soc/nvidia/tegra124/early_configs.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void setup_pinmux(void)
{
/* Write protect. */
gpio_input_pullup(GPIO(R1));
/* Recovery mode. */
gpio_input_pullup(GPIO(Q7));
/* Lid switch. */
gpio_input_pullup(GPIO(R4));
/* Power switch. */
gpio_input_pullup(GPIO(Q0));
/* Developer mode. */
gpio_input_pullup(GPIO(Q6));
/* EC in RW. */
gpio_input_pullup(GPIO(U4));
/* route PU4/5 to GMI to remove conflict w/PWM1/2. */
pinmux_set_config(PINMUX_GPIO_PU4_INDEX,
PINMUX_GPIO_PU4_FUNC_NOR); /* s/b GMI */
pinmux_set_config(PINMUX_GPIO_PU5_INDEX,
PINMUX_GPIO_PU5_FUNC_NOR); /* s/b GMI */
/* SOC and TPM reset GPIO, active low. */
gpio_output(GPIO(I5), 1);
/* SPI1 MOSI */
pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
/* SPI1 MISO */
pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
/* SPI1 SCLK */
pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
/* SPI1 CS0 */
pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
/* I2C3 (cam) clock. */
pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
/* I2C3 (cam) data. */
pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
/* switch unused pin to GPIO */
gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO);
}
static void configure_ec_spi_bus(void)
{
clock_configure_source(sbc1, CLK_M, 3000);
}
static void configure_tpm_i2c_bus(void)
{
clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
i2c_init(2);
}
void early_mainboard_init(void)
{
clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0);
setup_pinmux();
configure_ec_spi_bus();
configure_tpm_i2c_bus();
}

121
src/mainboard/google/nyan_blaze/romstage.c
View File

@ -30,8 +30,10 @@
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#include "sdram_configs.h" #include "sdram_configs.h"
#include <soc/nvidia/tegra/i2c.h> #include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/cache.h>
#include <soc/nvidia/tegra124/chip.h> #include <soc/nvidia/tegra124/chip.h>
#include <soc/nvidia/tegra124/clk_rst.h> #include <soc/nvidia/tegra124/clk_rst.h>
#include <soc/nvidia/tegra124/early_configs.h>
#include <soc/nvidia/tegra124/power.h> #include <soc/nvidia/tegra124/power.h>
#include <soc/nvidia/tegra124/sdram.h> #include <soc/nvidia/tegra124/sdram.h>
#include <soc/addressmap.h> #include <soc/addressmap.h>
@ -39,120 +41,12 @@
#include <soc/display.h> #include <soc/display.h>
#include <timestamp.h> #include <timestamp.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
enum {
L2CTLR_ECC_PARITY = 0x1 << 21,
L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6,
L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0,
L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0
};
enum {
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27,
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7,
L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3
};
/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */
static void configure_l2ctlr(void)
{
uint32_t val;
val = read_l2ctlr();
val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK);
val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 |
L2CTLR_ECC_PARITY);
write_l2ctlr(val);
}
/* Configures L2 Auxiliary Control Register for Cortex A15. */
static void configure_l2actlr(void)
{
uint32_t val;
val = read_l2actlr();
val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL |
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT |
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE);
write_l2actlr(val);
}
static void setup_pinmux(void)
{
// Write protect.
gpio_input_pullup(GPIO(R1));
// Recovery mode.
gpio_input_pullup(GPIO(Q7));
// Lid switch.
gpio_input_pullup(GPIO(R4));
// Power switch.
gpio_input_pullup(GPIO(Q0));
// Developer mode.
gpio_input_pullup(GPIO(Q6));
// EC in RW.
gpio_input_pullup(GPIO(U4));
// route PU4/5 to GMI to remove conflict w/PWM1/2.
pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); //s/b GMI
pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); //s/b GMI
// SOC and TPM reset GPIO, active low.
gpio_output(GPIO(I5), 1);
// SPI1 MOSI
pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 MISO
pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 SCLK
pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 CS0
pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// I2C3 (cam) clock.
pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// I2C3 (cam) data.
pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// switch unused pin to GPIO
gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO);
}
static void configure_ec_spi_bus(void)
{
clock_configure_source(sbc1, CLK_M, 3000);
}
static void configure_tpm_i2c_bus(void)
{
clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
i2c_init(2);
}
static void __attribute__((noinline)) romstage(void) static void __attribute__((noinline)) romstage(void)
{ {
timestamp_init(0); timestamp_init(0);
timestamp_add_now(TS_START_ROMSTAGE); timestamp_add_now(TS_START_ROMSTAGE);
configure_l2ctlr(); configure_l2_cache();
configure_l2actlr();
console_init(); console_init();
exception_init(); exception_init();
@ -191,13 +85,10 @@ static void __attribute__((noinline)) romstage(void)
cbmem_initialize_empty(); cbmem_initialize_empty();
// Enable additional peripherals we need for ROM stage. timestamp_init(0);
clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); timestamp_add(TS_START_ROMSTAGE, romstage_start_time);
setup_pinmux(); early_mainboard_init();
configure_ec_spi_bus();
configure_tpm_i2c_bus();
#if CONFIG_VBOOT2_VERIFY_FIRMWARE #if CONFIG_VBOOT2_VERIFY_FIRMWARE
vboot_create_handoff((void *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS); vboot_create_handoff((void *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS);

2
src/soc/nvidia/tegra124/Makefile.inc
View File

@ -32,6 +32,7 @@ verstage-y += ../tegra/i2c.c
verstage-y += ../tegra/pinmux.c verstage-y += ../tegra/pinmux.c
verstage-y += clock.c verstage-y += clock.c
verstage-y += i2c.c verstage-y += i2c.c
verstage-y += cache.c
romstage-y += cbfs.c romstage-y += cbfs.c
romstage-y += cbmem.c romstage-y += cbmem.c
@ -48,6 +49,7 @@ romstage-y += ../tegra/i2c.c
romstage-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c romstage-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c
romstage-y += ../tegra/pinmux.c romstage-y += ../tegra/pinmux.c
romstage-y += timer.c romstage-y += timer.c
romstage-y += cache.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-$(CONFIG_DRIVERS_UART) += uart.c
ramstage-y += cbfs.c ramstage-y += cbfs.c

79
src/soc/nvidia/tegra124/bootblock.c
View File

@ -25,81 +25,11 @@
#include <console/console.h> #include <console/console.h>
#include <soc/clock.h> #include <soc/clock.h>
#include <soc/nvidia/tegra/apbmisc.h> #include <soc/nvidia/tegra/apbmisc.h>
#include <soc/nvidia/tegra124/early_configs.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "pinmux.h" #include "pinmux.h"
#include "power.h" #include "power.h"
#include "verstage.h" #include "verstage.h"
#include <soc/addressmap.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void setup_pinmux(void)
{
// Write protect.
gpio_input_pullup(GPIO(R1));
// Recovery mode.
gpio_input_pullup(GPIO(Q7));
// Lid switch.
gpio_input_pullup(GPIO(R4));
// Power switch.
gpio_input_pullup(GPIO(Q0));
// Developer mode.
gpio_input_pullup(GPIO(Q6));
// EC in RW.
gpio_input_pullup(GPIO(U4));
// route PU4/5 to GMI to remove conflict w/PWM1/2.
pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR);
pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR);
// SOC and TPM reset GPIO, active low.
gpio_output(GPIO(I5), 1);
// SPI1 MOSI
pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 MISO
pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 SCLK
pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 CS0
pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// I2C3 (cam) clock.
pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// I2C3 (cam) data.
pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// switch unused pin to GPIO
gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO);
}
static void configure_ec_spi_bus(void)
{
clock_configure_source(sbc1, CLK_M, 3000);
}
static void configure_tpm_i2c_bus(void)
{
clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
i2c_init(2);
}
void main(void) void main(void)
{ {
@ -144,10 +74,7 @@ void main(void)
PINMUX_INPUT_ENABLE); PINMUX_INPUT_ENABLE);
if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) { if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) {
clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); early_mainboard_init();
setup_pinmux();
configure_ec_spi_bus();
configure_tpm_i2c_bus();
entry = (void *)verstage_vboot_main; entry = (void *)verstage_vboot_main;
} else } else
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage");

66
src/soc/nvidia/tegra124/cache.c Normal file
View File

@ -0,0 +1,66 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/cache.h>
#include <stdint.h>
#include "cache.h"
enum {
L2CTLR_ECC_PARITY = 0x1 << 21,
L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6,
L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0,
L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0
};
enum {
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27,
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7,
L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3
};
/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */
static void configure_l2ctlr(void)
{
uint32_t val;
val = read_l2ctlr();
val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK);
val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 |
L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | L2CTLR_ECC_PARITY);
write_l2ctlr(val);
}
/* Configures L2 Auxiliary Control Register for Cortex A15. */
static void configure_l2actlr(void)
{
uint32_t val;
val = read_l2actlr();
val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL |
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT |
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE);
write_l2actlr(val);
}
void configure_l2_cache(void)
{
configure_l2ctlr();
configure_l2actlr();
}

20
src/soc/nvidia/tegra124/cache.h Normal file
View File

@ -0,0 +1,20 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
void configure_l2_cache(void);

20
src/soc/nvidia/tegra124/early_configs.h Normal file
View File

@ -0,0 +1,20 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
void early_mainboard_init(void);

2
src/vendorcode/google/chromeos/Makefile.inc
View File

@ -101,7 +101,7 @@ VERSTAGE_LIB = $(obj)/vendorcode/google/chromeos/verstage.a
INCLUDES += -I$(VB_SOURCE)/firmware/2lib/include INCLUDES += -I$(VB_SOURCE)/firmware/2lib/include
INCLUDES += -I$(VB_SOURCE)/firmware/include INCLUDES += -I$(VB_SOURCE)/firmware/include
verstage-y += vboot_main.c fmap.c chromeos.c verstage-y += verstage.c fmap.c chromeos.c
verstage-y += antirollback.c vbnv_ec.c verstage-y += antirollback.c vbnv_ec.c
romstage-y += vboot_handoff.c romstage-y += vboot_handoff.c

48
src/vendorcode/google/chromeos/vboot_main.c → src/vendorcode/google/chromeos/verstage.c
View File

@ -3,6 +3,7 @@
#include <antirollback.h> #include <antirollback.h>
#include <arch/exception.h> #include <arch/exception.h>
#include <arch/stages.h> #include <arch/stages.h>
#include <soc/nvidia/tegra124/cache.h>
#include <cbfs.h> #include <cbfs.h>
#include <console/console.h> #include <console/console.h>
#include <console/vtxprintf.h> #include <console/vtxprintf.h>
@ -139,9 +140,8 @@ static int hash_body(struct vb2_context *ctx, struct vboot_region *fw_main)
/* Start the body hash */ /* Start the body hash */
rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size); rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
if (rv) { if (rv)
return rv; return rv;
}
/* Extend over the body */ /* Extend over the body */
while (expected_size) { while (expected_size) {
@ -162,9 +162,8 @@ static int hash_body(struct vb2_context *ctx, struct vboot_region *fw_main)
/* Check the result */ /* Check the result */
rv = vb2api_check_hash(ctx); rv = vb2api_check_hash(ctx);
if (rv) { if (rv)
return rv; return rv;
}
return VB2_SUCCESS; return VB2_SUCCESS;
} }
@ -230,44 +229,6 @@ static void enter_stage(struct cbfs_stage *stage)
stage_exit((void *)(uintptr_t)stage->entry); stage_exit((void *)(uintptr_t)stage->entry);
} }
enum {
L2CTLR_ECC_PARITY = 0x1 << 21,
L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6,
L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0,
L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0
};
enum {
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27,
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7,
L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3
};
/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */
static void configure_l2ctlr(void)
{
uint32_t val;
val = read_l2ctlr();
val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK);
val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 |
L2CTLR_ECC_PARITY);
write_l2ctlr(val);
}
/* Configures L2 Auxiliary Control Register for Cortex A15. */
static void configure_l2actlr(void)
{
uint32_t val;
val = read_l2actlr();
val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL |
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT |
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE);
write_l2actlr(val);
}
static void enable_cache(void) static void enable_cache(void)
{ {
mmu_init(); mmu_init();
@ -313,8 +274,7 @@ void __attribute__((noinline)) select_firmware(void)
int rv; int rv;
/* Do minimum to enable cache and run vboot at full speed */ /* Do minimum to enable cache and run vboot at full speed */
configure_l2ctlr(); configure_l2_cache();
configure_l2actlr();
console_init(); console_init();
exception_init(); exception_init();
enable_cache(); enable_cache();