broadwell: Fix devslp enable to use correct register

This was a merge error when I was pulling in some of the
code into this file I put it after the read of CAP2 but
before it is modified and written back.  In the end the
DEVSLP bits are getting set/cleared that need to but the
other bits in the register may be wrong.  Also when enabling
devslp set the devslp-present bit in each enabled port.

Also remove much of the 0:1f.2@0x98 setup and the attempt
to write (the write once) CAP register that is already
being written in the reference code.

BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus

Original-Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212308
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9110a42982183b2954c865abbf18e008a39c997c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7db5c7ccf619aa28856388dd40f59495ef6d7e77
Reviewed-on: http://review.coreboot.org/8958
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/soc/intel/broadwell/sata.c

@@ -48,6 +48,7 @@ static void sata_init(struct device *dev)
 	u32 reg32;
 	u8 *abar;
 	u16 reg16;
+	int port;
 
 	printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n");
 
@@ -82,18 +83,9 @@ static void sata_init(struct device *dev)
 
 	/* Setup register 98h */
 	reg32 = pci_read_config16(dev, 0x98);
-	reg32 |= 1 << 19;    /* BWG step 6 */
-	reg32 |= 1 << 22;    /* BWG step 5 */
-	reg32 &= ~(0x3f << 7);
-	reg32 |= 0x04 << 7;  /* BWG step 7 */
-	reg32 |= 1 << 20;    /* BWG step 8 */
-	reg32 &= ~(0x03 << 5);
-	reg32 |= 1 << 5;     /* BWG step 9 */
-	reg32 |= 1 << 18;    /* BWG step 10 */
-	reg32 |= 1 << 29;    /* BWG step 11 */
 	reg32 &= ~((1 << 31) | (1 << 30));
 	reg32 |= 1 << 23;
-	reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
+	reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */
 	pci_write_config32(dev, 0x98, reg32);
 
 	/* Setup register 9Ch */
@@ -111,20 +103,30 @@ static void sata_init(struct device *dev)
 	abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5));
 	printk(BIOS_DEBUG, "ABAR: %p\n", abar);
 
-	/* CAP (HBA Capabilities) : enable power management */
-	reg32 = read32(abar + 0x00);
-	reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
-	reg32 &= ~0x00020060; // clear SXS+EMS+PMS
-	reg32 |= (1 << 18);   // SAM: SATA AHCI MODE ONLY
-	write32(abar + 0x00, reg32);
-
 	/* PI (Ports implemented) */
 	write32(abar + 0x0c, config->sata_port_map);
 	(void) read32(abar + 0x0c); /* Read back 1 */
 	(void) read32(abar + 0x0c); /* Read back 2 */
 
 	/* CAP2 (HBA Capabilities Extended)*/
+	if (config->sata_devslp_disable) {
 		reg32 = read32(abar + 0x24);
+		reg32 &= ~(1 << 3);
+		write32(abar + 0x24, reg32);
+	} else {
+		/* Enable DEVSLP */
+		reg32 = read32(abar + 0x24);
+		reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
+		write32(abar + 0x24, reg32);
+
+		for (port = 0; port < 4; port++) {
+			if (!(config->sata_port_map & (1 << port)))
+				continue;
+			reg32 = read32(abar + 0x144 + (0x80 * port));
+			reg32 |= (1 << 1);	/* DEVSLP DSP */
+			write32(abar + 0x144 + (0x80 * port), reg32);
+		}
+	}
 
 	/*
 	 * Static Power Gating for unused ports
@@ -138,13 +140,6 @@ static void sata_init(struct device *dev)
 		reg32 |= (1 << 20) | (1 << 18);
 	RCBA32(0x3a84) = reg32;
 
-	/* Enable DEVSLP */
-	if (config->sata_devslp_disable)
-		reg32 &= ~(1 << 3);
-	else
-		reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
-	write32(abar + 0x24, reg32);
-
 	/* Set Gen3 Transmitter settings if needed */
 	if (config->sata_port0_gen3_tx)
 		pch_iobp_update(SATA_IOBP_SP0G3IR, 0,