broadwell: Fix devslp enable to use correct register
This was a merge error when I was pulling in some of the code into this file I put it after the read of CAP2 but before it is modified and written back. In the end the DEVSLP bits are getting set/cleared that need to but the other bits in the register may be wrong. Also when enabling devslp set the devslp-present bit in each enabled port. Also remove much of the 0:1f.2@0x98 setup and the attempt to write (the write once) CAP register that is already being written in the reference code. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212308 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9110a42982183b2954c865abbf18e008a39c997c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7db5c7ccf619aa28856388dd40f59495ef6d7e77 Reviewed-on: http://review.coreboot.org/8958 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
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@ -48,6 +48,7 @@ static void sata_init(struct device *dev)
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u32 reg32;
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u32 reg32;
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u8 *abar;
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u8 *abar;
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u16 reg16;
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u16 reg16;
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int port;
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printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n");
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printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n");
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@ -82,18 +83,9 @@ static void sata_init(struct device *dev)
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/* Setup register 98h */
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/* Setup register 98h */
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reg32 = pci_read_config16(dev, 0x98);
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reg32 = pci_read_config16(dev, 0x98);
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reg32 |= 1 << 19; /* BWG step 6 */
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reg32 |= 1 << 22; /* BWG step 5 */
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reg32 &= ~(0x3f << 7);
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reg32 |= 0x04 << 7; /* BWG step 7 */
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reg32 |= 1 << 20; /* BWG step 8 */
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reg32 &= ~(0x03 << 5);
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reg32 |= 1 << 5; /* BWG step 9 */
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reg32 |= 1 << 18; /* BWG step 10 */
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reg32 |= 1 << 29; /* BWG step 11 */
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reg32 &= ~((1 << 31) | (1 << 30));
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reg32 &= ~((1 << 31) | (1 << 30));
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reg32 |= 1 << 23;
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reg32 |= 1 << 23;
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reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
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reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */
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pci_write_config32(dev, 0x98, reg32);
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pci_write_config32(dev, 0x98, reg32);
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/* Setup register 9Ch */
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/* Setup register 9Ch */
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@ -111,20 +103,30 @@ static void sata_init(struct device *dev)
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abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5));
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abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5));
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printk(BIOS_DEBUG, "ABAR: %p\n", abar);
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printk(BIOS_DEBUG, "ABAR: %p\n", abar);
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/* CAP (HBA Capabilities) : enable power management */
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reg32 = read32(abar + 0x00);
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reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
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reg32 &= ~0x00020060; // clear SXS+EMS+PMS
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reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY
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write32(abar + 0x00, reg32);
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/* PI (Ports implemented) */
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/* PI (Ports implemented) */
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write32(abar + 0x0c, config->sata_port_map);
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write32(abar + 0x0c, config->sata_port_map);
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(void) read32(abar + 0x0c); /* Read back 1 */
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(void) read32(abar + 0x0c); /* Read back 1 */
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(void) read32(abar + 0x0c); /* Read back 2 */
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(void) read32(abar + 0x0c); /* Read back 2 */
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/* CAP2 (HBA Capabilities Extended)*/
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/* CAP2 (HBA Capabilities Extended)*/
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reg32 = read32(abar + 0x24);
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if (config->sata_devslp_disable) {
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reg32 = read32(abar + 0x24);
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reg32 &= ~(1 << 3);
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write32(abar + 0x24, reg32);
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} else {
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/* Enable DEVSLP */
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reg32 = read32(abar + 0x24);
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reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
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write32(abar + 0x24, reg32);
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for (port = 0; port < 4; port++) {
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if (!(config->sata_port_map & (1 << port)))
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continue;
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reg32 = read32(abar + 0x144 + (0x80 * port));
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reg32 |= (1 << 1); /* DEVSLP DSP */
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write32(abar + 0x144 + (0x80 * port), reg32);
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}
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}
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/*
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/*
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* Static Power Gating for unused ports
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* Static Power Gating for unused ports
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@ -138,13 +140,6 @@ static void sata_init(struct device *dev)
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reg32 |= (1 << 20) | (1 << 18);
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reg32 |= (1 << 20) | (1 << 18);
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RCBA32(0x3a84) = reg32;
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RCBA32(0x3a84) = reg32;
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/* Enable DEVSLP */
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if (config->sata_devslp_disable)
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reg32 &= ~(1 << 3);
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else
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reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
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write32(abar + 0x24, reg32);
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/* Set Gen3 Transmitter settings if needed */
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/* Set Gen3 Transmitter settings if needed */
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if (config->sata_port0_gen3_tx)
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if (config->sata_port0_gen3_tx)
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pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
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pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
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