soc/intel/icelake: Refactor pch_early_init() code
This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBUS init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. TEST=Able to build and boot ICL DE system. Change-Id: I4f0914242c3215f6bf76e41c468f544361a740d8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36627 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corp.
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* Copyright (C) 2018-2019 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -23,17 +23,13 @@
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#include <intelblocks/pcr.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/smbus.h>
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#include <intelblocks/tco.h>
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#include <soc/bootblock.h>
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#include <soc/espi.h>
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#include <soc/iomap.h>
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#include <soc/p2sb.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600
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#define PCR_PSFX_TO_SHDW_BAR0 0
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@ -94,7 +90,6 @@ void bootblock_pch_early_init(void)
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soc_config_pwrmbase();
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}
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static void soc_config_acpibase(void)
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{
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uint32_t pmc_reg_value;
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@ -163,12 +158,6 @@ void pch_early_init(void)
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*/
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soc_config_acpibase();
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/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
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tco_configure();
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/* Program SMBUS_BASE_ADDRESS and Enable it */
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smbus_common_init();
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/* Set up GPE configuration */
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pmc_gpe_init();
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@ -20,6 +20,7 @@
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void mainboard_memory_init_params(FSPM_UPD *mupd);
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void systemagent_early_init(void);
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void pch_init(void);
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/* Board type */
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enum board_type {
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@ -16,4 +16,5 @@
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romstage-y += fsp_params.c
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romstage-y += ../../../../cpu/intel/car/romstage.c
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romstage-y += romstage.c
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romstage-y += pch.c
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romstage-y += systemagent.c
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <intelblocks/smbus.h>
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#include <intelblocks/tco.h>
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#include <soc/romstage.h>
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void pch_init(void)
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{
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/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
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tco_configure();
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/* Program SMBUS_BASE_ADDRESS and Enable it */
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smbus_common_init();
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}
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@ -116,6 +116,8 @@ void mainboard_romstage_entry(void)
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/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
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systemagent_early_init();
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/* Program PCH init */
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pch_init();
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/* initialize Heci interface */
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heci_init(HECI1_BASE_ADDRESS);
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