soc/intel/icelake: Refactor pch_early_init() code

This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like
TCO configuration and SMBUS init into romstage/pch.c in order to maintain
only required chipset programming for bootblock and verstage.

TEST=Able to build and boot ICL DE system.

Change-Id: I4f0914242c3215f6bf76e41c468f544361a740d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36627
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/icelake/bootblock/pch.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2018 Intel Corp.
+ * Copyright (C) 2018-2019 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,17 +23,13 @@
 #include <intelblocks/pcr.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
-#include <intelblocks/smbus.h>
-#include <intelblocks/tco.h>
 #include <soc/bootblock.h>
-#include <soc/espi.h>
 #include <soc/iomap.h>
 #include <soc/p2sb.h>
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
-#include <soc/smbus.h>
 
 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x0600
 #define PCR_PSFX_TO_SHDW_BAR0	0
@@ -94,7 +90,6 @@ void bootblock_pch_early_init(void)
 	soc_config_pwrmbase();
 }
 
-
 static void soc_config_acpibase(void)
 {
 	uint32_t pmc_reg_value;
@@ -163,12 +158,6 @@ void pch_early_init(void)
 	 */
 	soc_config_acpibase();
 
-	/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
-	tco_configure();
-
-	/* Program SMBUS_BASE_ADDRESS and Enable it */
-	smbus_common_init();
-
 	/* Set up GPE configuration */
 	pmc_gpe_init();
 

src/soc/intel/icelake/include/soc/romstage.h

@@ -20,6 +20,7 @@
 
 void mainboard_memory_init_params(FSPM_UPD *mupd);
 void systemagent_early_init(void);
+void pch_init(void);
 
 /* Board type */
 enum board_type {

src/soc/intel/icelake/romstage/Makefile.inc

@@ -16,4 +16,5 @@
 romstage-y += fsp_params.c
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
+romstage-y += pch.c
 romstage-y += systemagent.c

src/soc/intel/icelake/romstage/pch.c

@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/smbus.h>
+#include <intelblocks/tco.h>
+#include <soc/romstage.h>
+
+void pch_init(void)
+{
+	/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
+	tco_configure();
+
+	/* Program SMBUS_BASE_ADDRESS and Enable it */
+	smbus_common_init();
+}

src/soc/intel/icelake/romstage/romstage.c

@@ -116,6 +116,8 @@ void mainboard_romstage_entry(void)
 
 	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
 	systemagent_early_init();
+	/* Program PCH init */
+	pch_init();
 	/* initialize Heci interface */
 	heci_init(HECI1_BASE_ADDRESS);