mb/intel/cedarisland_crb: Add Cedar Island CRB

Just a minimal set of board files needed to get it to boot
in 1 CPU mode.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: Ie2f944964e938d8026a6d5d8a22a8449199d08aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/intel/cedarisland_crb/Kconfig

@@ -0,0 +1,23 @@
+if BOARD_INTEL_CEDARISLAND_CRB
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_65536
+	select MAINBOARD_USES_FSP2_0
+	select SOC_INTEL_COOPERLAKE_SP
+	select SUPERIO_ASPEED_AST2400
+	select HAVE_ACPI_TABLES
+
+config MAINBOARD_DIR
+	string
+	default "intel/cedarisland_crb"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Cedar Island CRB"
+
+config FMDFILE
+	string
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+endif

src/mainboard/intel/cedarisland_crb/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_INTEL_CEDARISLAND_CRB
+	bool "Cedar Island CRB"

src/mainboard/intel/cedarisland_crb/Makefile.inc

@@ -0,0 +1 @@
+bootblock-y += bootblock.c

src/mainboard/intel/cedarisland_crb/acpi/platform.asl

@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+Name(\APC1, Zero) // IIO IOAPIC
+
+Name(\PICM, Zero) // IOAPIC/8259
+
+Method(_PIC, 1)
+{
+	Store(Arg0, PICM)
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}

src/mainboard/intel/cedarisland_crb/board.fmd

@@ -0,0 +1,11 @@
+FLASH@0xfc000000 64M {
+	SI_ALL@0x0 0x2fe8000 {
+		SI_DESC@0x0 0x1000
+		SI_GBE@0x1000 0x2000
+		SI_ME@0x3000 0x2fd5000
+		SI_PT@0x2fd8000 0x10000
+	}
+	FMAP@0x03000000 0x800
+	RW_MRC_CACHE@0x3000800 0x10000
+	COREBOOT(CBFS)@0x3010800
+}

src/mainboard/intel/cedarisland_crb/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Cedar Island CRB
+Category: eval
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y

src/mainboard/intel/cedarisland_crb/bootblock.c

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <bootblock_common.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Enable COM1 only */
+	pcr_write32(PID_DMI, 0x2770, 0);
+	pcr_write32(PID_DMI, 0x2774, 1);
+
+	/* Decode for SuperIO (0x2e) and COM1 (0x3f8) */
+	pci_mmio_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16));
+
+	const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1);
+	aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+}

src/mainboard/intel/cedarisland_crb/devicetree.cb

@@ -0,0 +1,54 @@
+chip soc/intel/xeon_sp/cpx
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on end # Host bridge
+		device pci 04.0 on end
+		device pci 04.1 on end
+		device pci 04.2 on end
+		device pci 04.3 on end
+		device pci 04.4 on end
+		device pci 04.5 on end
+		device pci 04.6 on end
+		device pci 04.7 on end
+		device pci 05.0 on end
+		device pci 05.2 on end
+		device pci 05.4 on end
+		device pci 08.0 on end
+		device pci 08.1 on end
+		device pci 08.2 on end
+		device pci 11.0 on end
+		device pci 11.1 on end
+		device pci 11.5 on end
+		device pci 14.0 on end
+		device pci 16.0 on end
+		device pci 16.1 on end
+		device pci 16.4 on end
+		device pci 17.0 on end
+		device pci 1c.0 on end
+		device pci 1c.4 on end
+		device pci 1f.2 on end
+		device pci 1f.4 on end
+		device pci 1f.5 on end
+
+		device pci 1f.0 on	# LPC/eSPI Interface
+			chip superio/common
+				device pnp 2e.0 on
+					chip superio/aspeed/ast2400
+						register "use_espi" = "1"
+						device pnp 2e.2 on	# SUART1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.3 on	# SUART2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+					end
+				end
+			end
+		end
+
+	end
+end

src/mainboard/intel/cedarisland_crb/dsdt.asl

@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <arch/acpi.h>
+#include <soc/iomap.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include "acpi/platform.asl"
+
+	Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 })
+	Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
+
+	Scope (\_SB)
+	{
+		Device (PCI0)
+		{
+			#include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl>
+			#include <soc/intel/common/block/acpi/acpi/lpc.asl>
+
+		}
+
+
+		Device (UNC0)
+		{
+			Name (_HID, EisaId ("PNP0A03"))
+			Name (_UID, 0x3F)
+			Method (_BBN, 0, NotSerialized)
+			{
+				Return (0xff)
+			}
+
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0xf)
+			}
+
+			Name (_CRS, ResourceTemplate ()
+			{
+				WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+					0x0000,             // Granularity
+					0x00FF,             // Range Minimum
+					0x00FF,             // Range Maximum
+					0x0000,             // Translation Offset
+					0x0001,             // Length
+					,, )
+			})
+
+		}
+	}
+
+}