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soc/amd/cezanne/include/data_fabric: add DF PCI config map register 

PPR #56569 Rev 3.04 was used as a reference.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idfac7d996c6de9ea7c6adf2760de0ad97ffb9ec0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Felix Held 2023-08-08 01:41:55 +02:00
parent 001bf0c7a8
commit 1b39cb1ba0
1 changed files with 19 additions and 0 deletions
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19
src/soc/amd/cezanne/include/soc/data_fabric.h
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@ -8,6 +8,25 @@
#define IOMS0_FABRIC_ID 10 #define IOMS0_FABRIC_ID 10
#define DF_PCI_CFG_MAP0 DF_REG_ID(0, 0xa0)
#define DF_PCI_CFG_MAP_COUNT 8
#define DF_PCI_CFG_MAP(reg) (DF_PCI_CFG_MAP0 + (reg) * sizeof(uint32_t))
union df_pci_cfg_map {
struct {
uint32_t re : 1; /* [ 0.. 0] */
uint32_t we : 1; /* [ 1.. 1] */
uint32_t : 2; /* [ 2.. 3] */
uint32_t dst_fabric_id : 10; /* [ 4..13] */
uint32_t : 2; /* [14..15] */
uint32_t bus_num_base : 8; /* [16..23] */
uint32_t bus_num_limit : 8; /* [24..31] */
};
uint32_t raw;
};
#define DF_IO_BASE0 DF_REG_ID(0, 0xc0) #define DF_IO_BASE0 DF_REG_ID(0, 0xc0)
#define DF_IO_LIMIT0 DF_REG_ID(0, 0xc4) #define DF_IO_LIMIT0 DF_REG_ID(0, 0xc4)