From 1b414d14fda03e7e579ed20c8a874b3a97c4b427 Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Tue, 16 Jan 2024 15:36:46 +0530 Subject: [PATCH] =?UTF-8?q?mb/google/rex/var/rex:=20Set=20TCC=20to=20100?= =?UTF-8?q?=C2=B0C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature for rex. BUG=b:270664854 TEST=Build, boot and test on rex with value under sysfs /sys/bus/pci/devices/0000:00:04.0/tcc_offset_degree_celsius Change-Id: I9012984016ab3213102214025d6d8dc07c5d8974 Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/79992 Reviewed-by: Subrata Banik Reviewed-by: Peter Ou Tested-by: build bot (Jenkins) --- src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 9f868406a1..58c1719b48 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -45,6 +45,9 @@ chip soc/intel/meteorlake # DPTF enable register "dptf_enable" = "1" + # Setting TCC of 100C = Tj max (110) - TCC_Offset (10) + register "tcc_offset" = "10" + # Enable CNVi BT register "cnvi_bt_core" = "true"