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soc/intel/alderlake: RPL-P power limits and VR settings

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This patch sets the Power Limits and Voltage Regulator settings for
three RaptorLake SKUs (45W, 28W and 15W) following the guidance from
document 686872 (June 7th edition).

BUG=b:237809660
TEST=Power Limit and VR serial logs review + debug instrumentation
     SKUs successfully booted

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I7e9d4039615e6c33b869c6243efbfeb2259ac219
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65582
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Jeremy Compostella 2022-06-17 15:18:02 -07:00 committed by Felix Held
parent 7c60068b23
commit 1b44c81d3d
4 changed files with 63 additions and 1 deletions
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6
src/soc/intel/alderlake/chip.h
View file

@ -42,6 +42,9 @@ enum soc_intel_alderlake_power_limits {
ADL_S_642_125W_CORE,
ADL_S_602_35W_CORE,
ADL_S_602_65W_CORE,
RPL_P_682_642_482_45W_CORE,
RPL_P_682_482_282_28W_CORE,
RPL_P_282_242_142_15W_CORE,
ADL_POWER_LIMITS_COUNT
};
@ -90,6 +93,9 @@ static const struct {
{ PCI_DID_INTEL_ADL_S_ID_8, ADL_S_642_125W_CORE, TDP_125W },
{ PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_35W_CORE, TDP_35W },
{ PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_65W_CORE, TDP_65W },
{ PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W },
{ PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W },
{ PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W },
};
/* Types of display ports */

18
src/soc/intel/alderlake/chipset.cb
View file

@ -66,6 +66,24 @@ chip soc/intel/alderlake
.tdp_pl4 = 78,
}"
register "power_limits_config[RPL_P_682_642_482_45W_CORE]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 115,
.tdp_pl4 = 210,
}"
register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{
.tdp_pl1_override = 28,
.tdp_pl2_override = 64,
.tdp_pl4 = 126,
}"
register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 114,
}"
# NOTE: if any variant wants to override this value, use the same format
# as register "common_soc_config.pch_thermal_trip" = "value", instead of
# putting it under register "common_soc_config" in overridetree.cb file.

6
src/soc/intel/alderlake/fsp_params.c
View file

@ -490,7 +490,8 @@ static unsigned int get_aspm_control(enum ASPM_control ctl)
return ctl - 1;
}
/* This function returns the VccIn Aux Imon IccMax values for ADL-P and ADL-S SKU's */
/* This function returns the VccIn Aux Imon IccMax values for ADL and RPL
SKU's */
static uint16_t get_vccin_aux_imon_iccmax(void)
{
struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
@ -507,6 +508,9 @@ static uint16_t get_vccin_aux_imon_iccmax(void)
case PCI_DID_INTEL_ADL_P_ID_8:
case PCI_DID_INTEL_ADL_P_ID_9:
case PCI_DID_INTEL_ADL_P_ID_10:
case PCI_DID_INTEL_RPL_P_ID_1:
case PCI_DID_INTEL_RPL_P_ID_2:
case PCI_DID_INTEL_RPL_P_ID_3:
tdp = get_cpu_tdp();
if (tdp == TDP_45W)
return ICC_MAX_TDP_45W;

34
src/soc/intel/alderlake/vr_config.c
View file

@ -68,6 +68,28 @@
* +----------------+-----------+-------+-------+---------+-------------+----------+
*/
/*
* VR Configurations for IA and GT domains for RPL-P SKU's.
* Per doc#686872 RPL UPH PDG - 2022, June 7th edition
*
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
* | | |(mOhms)|(mOhms)| (A) | (A) | (msec) |
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | RPL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 86 | 28000 |
* + +-----------+-------+-------+---------+-------------+----------+
* | | GT | 3.2 | 3.2 | 55 | 86 | 28000 |
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | RPL-P 482(28W) | IA | 2.3 | 2.3 | 102 | 54 | 28000 |
* + +-----------+-------+-------+---------+-------------+----------+
* | | GT | 3.2 | 3.2 | 55 | 54 | 28000 |
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | RPL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 41 | 28000 |
* + +-----------+-------+-------+---------+-------------+----------+
* | | GT | 3.2 | 3.2 | 55 | 41 | 28000 |
* +----------------+-----------+-------+-------+---------+-------------+----------+
*/
struct vr_lookup {
uint16_t mchid;
uint8_t tdp;
@ -104,6 +126,9 @@ static const struct vr_lookup vr_config_ll[] = {
{ PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
};
static const struct vr_lookup vr_config_icc[] = {
@ -122,6 +147,9 @@ static const struct vr_lookup vr_config_icc[] = {
{ PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
{ PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) },
{ PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 55) },
};
static const struct vr_lookup vr_config_tdc_timewindow[] = {
@ -140,6 +168,9 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = {
{ PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
};
static const struct vr_lookup vr_config_tdc_currentlimit[] = {
@ -158,6 +189,9 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
{ PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) },
{ PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) },
{ PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(54, 54) },
{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) },
};
void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,