soc/intel/braswell: use common Intel ACPI hardware definitions

Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Ia3860fe9e5229917881696e08418c3fd5fb64ecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>

src/soc/intel/braswell/Kconfig

@@ -7,6 +7,7 @@ if SOC_INTEL_BRASWELL
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
+	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ARCH_BOOTBLOCK_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32

src/soc/intel/braswell/elog.c

@@ -67,7 +67,7 @@ static void log_wake_events(const struct chipset_power_state *ps)
 
 	if (ps->pm1_sts & WAK_STS)
 		elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
-				    acpi_slp_type == 3 ? 3 : 5);
+				    acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5);
 
 	if (ps->pm1_sts & PWRBTN_STS)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);

src/soc/intel/braswell/include/soc/pm.h

@@ -17,6 +17,7 @@
 #ifndef _SOC_PM_H_
 #define _SOC_PM_H_
 
+#include <arch/acpi.h>
 
 #define IOCOM1		0x3f8
 
@@ -148,14 +149,6 @@
 #define   GBL_EN	(1 << 5)
 #define   TMROF_EN	(1 << 0)
 #define PM1_CNT			0x04
-#define   SLP_EN	(1 << 13)
-#define   SLP_TYP_SHIFT	10
-#define   SLP_TYP	(7 << SLP_TYP_SHIFT)
-#define    SLP_TYP_S0	0
-#define    SLP_TYP_S1	1
-#define    SLP_TYP_S3	5
-#define    SLP_TYP_S4	6
-#define    SLP_TYP_S5	7
 #define   GBL_RLS	(1 << 2)
 #define   BM_RLD	(1 << 1)
 #define   SCI_EN	(1 << 0)
@@ -214,11 +207,6 @@
 #	define TCO_TMR_HALT	(1 << 11)
 #define TCO_TMR			0x70
 
-/* Generic sleep state types */
-#define SLEEP_STATE_S0		0
-#define SLEEP_STATE_S3		3
-#define SLEEP_STATE_S5		5
-
 #if !defined(__ASSEMBLER__) && !defined(__ACPI__)
 
 /* Track power state from reset to log events. */

src/soc/intel/braswell/lpc_init.c

@@ -114,8 +114,8 @@ void lpc_init(void)
 	pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
 
 	if (pm1_sts & WAK_STS)
-		slp_type = (pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT;
+		slp_type = acpi_sleep_from_pm1(pm1_cnt);
 
-	if ((slp_type == SLP_TYP_S3) || (slp_type == SLP_TYP_S5))
+	if ((slp_type == ACPI_S3) || (slp_type == ACPI_S5))
 		lpc_gpio_config(RESUME_CYCLE);
 }

src/soc/intel/braswell/romstage/romstage.c

@@ -137,17 +137,16 @@ struct chipset_power_state *fill_power_state(void)
 int chipset_prev_sleep_state(struct chipset_power_state *ps)
 {
 	/* Default to S0. */
-	int prev_sleep_state = SLEEP_STATE_S0;
+	int prev_sleep_state = ACPI_S0;
 
 	if (ps->pm1_sts & WAK_STS) {
-		switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
+		switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
-	#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+		case ACPI_S3:
-		case SLP_TYP_S3:
+			if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
-			prev_sleep_state = SLEEP_STATE_S3;
+				prev_sleep_state = ACPI_S3;
 			break;
-	#endif
+		case ACPI_S5:
-		case SLP_TYP_S5:
+			prev_sleep_state = ACPI_S5;
-			prev_sleep_state = SLEEP_STATE_S5;
 			break;
 		}
 
@@ -156,7 +155,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
 	}
 
 	if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR))
-		prev_sleep_state = SLEEP_STATE_S5;
+		prev_sleep_state = ACPI_S5;
 
 	return prev_sleep_state;
 }

src/soc/intel/braswell/smihandler.c

@@ -146,15 +146,15 @@ static void southbridge_smi_sleep(void)
 	/* Figure out SLP_TYP */
 	reg32 = inl(pmbase + PM1_CNT);
 	printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
-	slp_typ = (reg32 >> 10) & 7;
+	slp_typ = acpi_sleep_from_pm1(reg32);
 
 	/* Do any mainboard sleep handling */
-	mainboard_smi_sleep(slp_typ-2);
+	mainboard_smi_sleep(slp_typ);
 
 #if IS_ENABLED(CONFIG_ELOG_GSMI)
 	/* Log S3, S4, and S5 entry */
-	if (slp_typ >= 5)
+	if (slp_typ >= ACPI_S3)
-		elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
+		elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
 #endif
       /* Clear pending GPE events */
 	clear_gpe_status();
@@ -162,22 +162,22 @@ static void southbridge_smi_sleep(void)
 	/* Next, do the deed. */
 
 	switch (slp_typ) {
-	case SLP_TYP_S0:
+	case ACPI_S0:
 		printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
 		break;
-	case SLP_TYP_S1:
+	case ACPI_S1:
 		printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n");
 		break;
-	case SLP_TYP_S3:
+	case ACPI_S3:
 		printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
 
 		/* Invalidate the cache before going to S3 */
 		wbinvd();
 		break;
-	case SLP_TYP_S4:
+	case ACPI_S4:
 		printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
 		break;
-	case SLP_TYP_S5:
+	case ACPI_S5:
 		printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
 
 		/* Disable all GPE */
@@ -195,7 +195,7 @@ static void southbridge_smi_sleep(void)
 		read32((void *)(0xfed88000 + 0x0200)));
 
 	/* Tri-state specific GPIOS to avoid leakage during S3/S5 */
-	if ((slp_typ == SLP_TYP_S3) || (slp_typ == SLP_TYP_S5))
+	if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))
 		tristate_gpios(PAD_CONTROL_REG0_TRISTATE);
 
 	/*
@@ -206,7 +206,7 @@ static void southbridge_smi_sleep(void)
 	enable_pm1_control(SLP_EN);
 
 	/* Make sure to stop executing code here for S3/S4/S5 */
-	if (slp_typ > 1)
+	if (slp_typ >= ACPI_S3)
 		hlt();
 
 	/*