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src/soc/intel/cannonlake: Add _PRW for CNVi 

Add _PRW so that wake on WLAN feature works.

TEST=Boot to OS and check if WLAN device wakes host.

Change-Id: Id6689754d1c4100615e4e4ae5a7f9846f4bf785f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Bora Guvendik 2017-11-27 12:14:58 -08:00 committed by Aaron Durbin
parent 562b168a77
commit 1b75994b4e
3 changed files with 48 additions and 9 deletions
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32
src/soc/intel/cannonlake/acpi/cnvi.asl Normal file
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@ -0,0 +1,32 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/pm.h>
/* CNVi Controller 0:14.3 */
Device (CNVI) {
Name(_ADR, 0x00140003)
Name (_S3D, 3) /* D3 supported in S3 */
Name (_S0W, 3) /* D3 can wake device in S0 */
Name (_S3W, 3) /* D3 can wake system from S3 */
Name (_PRW, Package() { PME_B0_EN_BIT, 3 })
Method (_STA, 0)
{
Return (0xF)
}
}

3
src/soc/intel/cannonlake/acpi/southbridge.asl
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@ -45,3 +45,6 @@
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
/* CNVi */
#include "cnvi.asl"

22
src/soc/intel/cannonlake/include/soc/pm.h
View File

@ -17,14 +17,6 @@
#ifndef _SOC_PM_H_
#define _SOC_PM_H_
#include <arch/acpi.h>
#include <arch/io.h>
#include <compiler.h>
#include <soc/gpe.h>
#include <soc/iomap.h>
#include <soc/smbus.h>
#include <soc/pmc.h>
#define PM1_STS 0x00
#define WAK_STS (1 << 15)
#define PCIEXPWAK_STS (1 << 14)
@ -116,7 +108,8 @@
#define WADT_EN (1 << 18)
#define GPIO_T2_EN (1 << 15)
#define ESPI_EN (1 << 14)
#define PME_B0_EN (1 << 13)
#define PME_B0_EN_BIT 13
#define PME_B0_EN (1 << PME_B0_EN_BIT)
#define ME_SCI_EN (1 << 12)
#define PME_EN (1 << 11)
#define BATLOW_EN (1 << 10)
@ -145,6 +138,16 @@
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
#if !defined(__ACPI__)
#include <arch/acpi.h>
#include <arch/io.h>
#include <compiler.h>
#include <soc/gpe.h>
#include <soc/iomap.h>
#include <soc/smbus.h>
#include <soc/pmc.h>
struct chipset_power_state {
uint16_t pm1_sts;
uint16_t pm1_en;
@ -168,4 +171,5 @@ uint16_t smbus_tco_regs(void);
/* Set the DISB after DRAM init */
void pmc_set_disb(void);
#endif /* !defined(__ACPI__) */
#endif