diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c
index 2f35c818f5..6c5f9c957f 100644
--- a/src/mainboard/lenovo/x201/mainboard.c
+++ b/src/mainboard/lenovo/x201/mainboard.c
@@ -18,6 +18,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <arch/acpi.h>
 #include <arch/io.h>
 #include <delay.h>
 #include <string.h>
@@ -90,7 +91,6 @@ static void fill_ssdt(device_t device)
 
 static void mainboard_enable(device_t dev)
 {
-	device_t dev0;
 	u16 pmbase;
 
 	dev->ops->init = mainboard_init;
@@ -110,8 +110,7 @@ static void mainboard_enable(device_t dev)
 			  0x10);
 
 	/* If we're resuming from suspend, blink suspend LED */
-	dev0 = dev_find_slot(0, PCI_DEVFN(0, 0));
-	if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
+	if (acpi_is_wakeup_s3())
 		ec_write(0x0c, 0xc7);
 
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2);
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 2bfa19c412..107cc46fc8 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -26,6 +26,7 @@
 #include <cpu/x86/lapic.h>
 #include <lib.h>
 #include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
@@ -277,20 +278,13 @@ void mainboard_romstage_entry(unsigned long bist)
 		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 	}
 
-#if CONFIG_HAVE_ACPI_RESUME
-	/* If there is no high memory area, we didn't boot before, so
-	 * this is not a resume. In that case we just create the cbmem toc.
-	 */
-	if (s3resume) {
-		acpi_prepare_for_resume();
 
-		/* Magic for S3 resume */
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
-	} else {
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+	romstage_handoff_init(s3resume);
+
+	if (s3resume)
+		acpi_prepare_for_resume();
+	else
 		quick_ram_check();
-	}
-#endif
 
 #if CONFIG_LPC_TPM
 	init_tpm(s3resume);
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index 92ee021caf..42b345ed81 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -26,6 +26,7 @@
 #include <cpu/x86/lapic.h>
 #include <lib.h>
 #include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
@@ -267,18 +268,11 @@ void mainboard_romstage_entry(unsigned long bist)
 		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 	}
 
-#if CONFIG_HAVE_ACPI_RESUME
-	/* If there is no high memory area, we didn't boot before, so
-	 * this is not a resume. In that case we just create the cbmem toc.
-	 */
-	if (s3resume) {
-		acpi_prepare_for_resume();
 
-		/* Magic for S3 resume */
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
-	} else {
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+	romstage_handoff_init(s3resume);
+
+	if (s3resume)
+		acpi_prepare_for_resume();
+	else
 		quick_ram_check();
-	}
-#endif
 }
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index f20ef2da4b..ee8dd00a82 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -222,10 +222,6 @@ enum {
 #define D0F0_TOLUD 0xb0
 #define D0F0_SKPD 0xdc /* Scratchpad Data */
 
-#define SKPAD_ACPI_S3_MAGIC	0xcafed00d
-#define SKPAD_NORMAL_BOOT_MAGIC	0xcafebabe
-
-
 #define D0F0_CAPID0 0xe0
 
 #define TSEG		0xac	/* TSEG base */
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 779e49cd54..8a64aa3697 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -280,26 +280,6 @@ static void northbridge_init(struct device *dev)
 	MCHBAR32(0x5500) = 0x00100001;
 }
 
-static void northbridge_enable(device_t dev)
-{
-#if CONFIG_HAVE_ACPI_RESUME
-	switch (pci_read_config32(dev, SKPAD)) {
-	case 0xcafebabe:
-		printk(BIOS_DEBUG, "Normal boot.\n");
-		acpi_slp_type = 0;
-		break;
-	case 0xcafed00d:
-		printk(BIOS_DEBUG, "S3 Resume.\n");
-		acpi_slp_type = 3;
-		break;
-	default:
-		printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
-		acpi_slp_type = 0;
-		break;
-	}
-#endif
-}
-
 static struct pci_operations intel_pci_ops = {
 	.set_subsystem = intel_set_subsystem,
 };
@@ -309,7 +289,6 @@ static struct device_operations mc_ops = {
 	.set_resources = mc_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init = northbridge_init,
-	.enable = northbridge_enable,
 	.acpi_fill_ssdt_generator = generate_cpu_entries,
 	.scan_bus = 0,
 	.ops_pci = &intel_pci_ops,