From 1b79b86defc08143c5f6870a40ddbf25b66c0370 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 20 Oct 2019 00:01:58 +0200 Subject: [PATCH] mb/supermicro/x11-lga1151-series: enable SLP_S0 as vendor does MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This enables SLP_S0 for x11 boards. Change-Id: I7240ed631bf72b1d3c9ea887da43772781c80b45 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36141 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph --- src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index b94bee8d90..1b9dc271b6 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -92,7 +92,8 @@ chip soc/intel/skylake # LPC register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + register "s0ix_enable" = "1" register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"