mb/google/guybrush: Setup EC_IN_RW GPIO and export to payload

EC_IN_RW_OD signal is routed from Google Security Chip to GPIO_91 in the
upcoming hardware build. The existing SD_EX_PRSNT signal is dropped in
the upcoming hardware build because SD7 support is dropped. Export the
EC_IN_RW GPIO for use by payload.

BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that the device can boot
successfully in both recovery and normal mode.

Cq-Depend: chromium:3043702
Change-Id: I8986ba007a2d899c510be61664d90430b8d2d384
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56493
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/guybrush/chromeos.c

@@ -10,6 +10,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 	struct lb_gpio chromeos_gpios[] = {
 		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
 		{-1, ACTIVE_HIGH, 0, "power"},
+		{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
 	};
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }

src/mainboard/google/guybrush/variants/baseboard/gpio.c

@@ -105,7 +105,7 @@ static const struct soc_amd_gpio base_gpio_table[] = {
 	PAD_GPI(GPIO_89, PULL_NONE),
 	/* HP_INT_ODL */
 	PAD_GPI(GPIO_90, PULL_NONE),
-	/* SD_EX_PRSNT_L */
+	/* SD_EX_PRSNT_L(Guybrush BoardID 1 only) / EC_IN_RW_OD */
 	PAD_GPI(GPIO_91, PULL_NONE),
 	/* CLK_REQ0_L */
 	PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),

src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h

@@ -7,5 +7,7 @@
 
 /* SPI Write protect */
 #define CROS_WP_GPIO GPIO_67
+/* GPIO to identify whether EC is in RO or RW */
+#define GPIO_EC_IN_RW GPIO_91
 
 #endif /* __BASEBOARD_GPIO_H__ */