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drivers/genesyslogic/gl9763e: Add HS400ES compatibility settings 

By default, the HS400 mode of GL9763E is slow mode (150MHz).
Therefore, the slow mode is disabled for HS400 running at 200MHz.
For eMMCs such as Hynix (H26M74002HMR) on HS400, adjust the internal
Rx latch dealy of HS400 to have better compatibility.

Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I84844c2432d4223d9929182c5c430915e52875b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Ben Chuang 2021-01-04 15:39:28 +08:00 committed by Tim Wawrzynczak
parent cc5aab02df
commit 1b7f63ff8a
2 changed files with 9 additions and 0 deletions
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4
src/drivers/genesyslogic/gl9763e/gl9763e.c
View File

@ -33,6 +33,10 @@ static void gl9763e_init(struct device *dev)
/* Set clock source for RX path */
pci_update_config32(dev, SD_CLKRX_DLY, ~CLK_SRC_MASK, AFTER_OUTPUT_BUFF);
}
/* Modify DS delay */
pci_update_config32(dev, SD_CLKRX_DLY, ~HS400_RX_DELAY_MASK, HS400_RX_DELAY);
/* Disable Slow mode */
pci_and_config32(dev, EMMC_CTL, ~SLOW_MODE);
/* Set VHS to read-only */
pci_update_config32(dev, VHS, ~VHS_REV_MASK, VHS_REV_R);
}

5
src/drivers/genesyslogic/gl9763e/gl9763e.h
View File

@ -18,6 +18,9 @@
#define PLL_CTL 0x938
#define PLL_CTL_SSC BIT(19)
#define EMMC_CTL 0x960
#define SLOW_MODE BIT(3)
#define PLL_CTL_2 0x93C
#define PLL_CTL_2_MAX_SSC_MASK (0xFFFF << 16)
#define MAX_SSC_30000PPM (0xF5C3 << 16)
@ -29,3 +32,5 @@
#define SD_CLKRX_DLY 0x934
#define CLK_SRC_MASK (0x3 << 24)
#define AFTER_OUTPUT_BUFF (0x0 << 24)
#define HS400_RX_DELAY_MASK (0xF << 28)
#define HS400_RX_DELAY (0x5 << 28)