diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 7c8b6387a2..94a101f501 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -117,6 +117,19 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 	silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
 	silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
 
+	if (cfg->emmc_tx_cmd_cntl != 0)
+		silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
+	if (cfg->emmc_tx_data_cntl1 != 0)
+		silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1;
+	if (cfg->emmc_tx_data_cntl2 != 0)
+		silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2;
+	if (cfg->emmc_rx_cmd_data_cntl1 != 0)
+		silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1;
+	if (cfg->emmc_rx_strobe_cntl != 0)
+		silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl;
+	if (cfg->emmc_rx_cmd_data_cntl2 != 0)
+		silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
+
 	/* Our defaults may not match FSP defaults, so set them explicitly */
 	silconfig->AcpiBase = ACPI_PMIO_BASE;
 	/* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 3d9f5bd2d7..ef82c53dee 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -40,6 +40,40 @@ struct soc_intel_apollolake_config {
 	uint8_t pcie_rp4_clkreq_pin;
 	uint8_t pcie_rp5_clkreq_pin;
 
+	/* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
+	 * [6:0] SDR mode Number of dealy elements.Each = 125pSec.
+	 */
+	uint32_t emmc_tx_cmd_cntl;
+
+	/* [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
+	 * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
+	 */
+	uint32_t emmc_tx_data_cntl1;
+
+	/* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
+	 * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
+	 * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
+	 * [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec.
+	 */
+	uint32_t emmc_tx_data_cntl2;
+
+	/* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
+	 * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
+	 * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
+	 * [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec.
+	 */
+	uint32_t emmc_rx_cmd_data_cntl1;
+
+	/* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
+	 * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
+	 */
+	uint32_t emmc_rx_strobe_cntl;
+
+	/* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
+	 * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
+	 */
+	uint32_t emmc_rx_cmd_data_cntl2;
+
 	/* Configure serial IRQ (SERIRQ) line. */
 	enum serirq_mode serirq_mode;