implement usb2 termination and dpll delay setting for vt8237r
Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/385 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config {
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/* 1 = 80-pin cable, 0 = 40-pin cable */
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u8 ide0_80pin_cable;
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u8 ide1_80pin_cable;
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u8 usb2_termination_set;
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u8 usb2_termination_a;
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u8 usb2_termination_b;
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u8 usb2_termination_c;
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u8 usb2_termination_d;
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u8 usb2_termination_e;
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u8 usb2_termination_f;
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u8 usb2_termination_g;
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u8 usb2_termination_h;
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u8 usb2_dpll_set;
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u8 usb2_dpll_delay;
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};
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#endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */
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@ -22,6 +22,7 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "chip.h"
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#include "vt8237r.h"
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#if CONFIG_EPIA_VT8237R_INIT
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@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev)
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static void usb_ii_init(struct device *dev)
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{
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struct southbridge_via_vt8237r_config *cfg;
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#if CONFIG_EPIA_VT8237R_INIT
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u8 reg8;
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@ -112,6 +114,28 @@ static void usb_ii_init(struct device *dev)
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pci_write_config16(dev, 0x06, 0x7A10);
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#endif
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cfg = dev->chip_info;
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if (cfg) {
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if (cfg->usb2_termination_set) {
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/* High Speed Port Pad Termination Resistor Fine Tune */
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pci_write_config8(dev, 0x5a, cfg->usb2_termination_c |
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(cfg->usb2_termination_d << 4));
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pci_write_config8(dev, 0x5b, cfg->usb2_termination_a |
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(cfg->usb2_termination_b << 4));
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pci_write_config8(dev, 0x5d, cfg->usb2_termination_e |
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(cfg->usb2_termination_f << 4));
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pci_write_config8(dev, 0x5e, cfg->usb2_termination_g |
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(cfg->usb2_termination_h << 4));
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}
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if (cfg->usb2_dpll_set) {
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/* Delay DPLL Input Data Control */
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pci_write_config8(dev, 0x5c,
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(pci_read_config8(dev, 0x5c) & ~0x70) |
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(cfg->usb2_dpll_delay << 4));
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}
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}
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}
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static void vt8237_usb_ii_read_resources(struct device *dev)
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