diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index c001dbeb86..fdfcd61f51 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -275,18 +275,18 @@ chip soc/intel/apollolake
 	# RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8.
 	# The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY.
 	# uint8 RegOrValue, RegAndValue, PmicReadReg
-	# RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0xff);
-	# RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0xff);
+	# RegOrValue = (UINT8)((pmic_pmc_ipc_ctrl >> 8) & 0xff);
+	# RegAndValue = (UINT8)(pmic_pmc_ipc_ctrl & 0xff);
 	# PmicReadReg &= RegAndValue;
 	# PmicReadReg |= RegOrValue;
 	# PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field
 	# and D[7:3] RSVD will not be impacted.
 
-	# Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay
+	# Configure pmic_pmc_ipc_ctrl for PMC to program PMIC PCH_PWROK delay
 	# from 100ms to 10ms.
 	# PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms,
 	#                  101=50ms, 110=75ms, 111=100ms (default)
-	register "PmicPmcIpcCtrl" = "0x5e4302f8"
+	register "pmic_pmc_ipc_ctrl" = "0x5e4302f8"
 
 	# FSP UPD to modify the Integrated Filter (IF) value
 	# Set it to default value: 0x12
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 76a6cc4d1f..57aa0858f4 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -602,7 +602,7 @@ static void glk_fsp_silicon_init_params_cb(
 	 * improve boot performance, configure PmicPmcIpcCtrl for PMC to program
 	 * PMIC PCH_PWROK delay.
 	 */
-	silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl;
+	silconfig->PmicPmcIpcCtrl = cfg->pmic_pmc_ipc_ctrl;
 
 	/*
 	 * Options to disable XHCI Link Compliance Mode.
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index fa22415dcb..88ec1ff21b 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -178,7 +178,7 @@ struct soc_intel_apollolake_config {
 	 * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
 	 * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
 	 */
-	uint32_t PmicPmcIpcCtrl;
+	uint32_t pmic_pmc_ipc_ctrl;
 
 	/* Options to disable XHCI Link Compliance Mode. Default is FALSE to not
 	 * disable Compliance Mode. Set TRUE to disable Compliance Mode.