diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index 9a8c8efdee..a838146c84 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -35,31 +35,22 @@
 static void lpc_init(struct device *dev)
 {
 	u8 byte;
-	u32 dword;
-
-	/*
-	 * Enable the LPC Controller
-	 * SMBus register 0x64 is not defined in public datasheet.
-	 */
-	dword = pci_read_config32(SOC_SMBUS_DEV, 0x64);
-	dword |= 1 << 20;
-	pci_write_config32(SOC_SMBUS_DEV, 0x64, dword);
 
 	/* Initialize isa dma */
 	isa_dma_init();
 
 	/* Enable DMA transaction on the LPC bus */
-	byte = pci_read_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL);
+	byte = pci_read_config8(dev, LPC_PCI_CONTROL);
 	byte |= LEGACY_DMA_EN;
-	pci_write_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL, byte);
+	pci_write_config8(dev, LPC_PCI_CONTROL, byte);
 
 	/* Disable the timeout mechanism on LPC */
-	byte = pci_read_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
+	byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
 	byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE;
-	pci_write_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, byte);
+	pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte);
 
 	/* Disable LPC MSI Capability */
-	byte = pci_read_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS);
+	byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS);
 	/* BIT 1 is not defined in public datasheet. */
 	byte &= ~(1 << 1);
 
@@ -69,15 +60,15 @@ static void lpc_init(struct device *dev)
 	 * interrupt and visit LPC.
 	 */
 	byte &= ~LPC_NOHOG;
-	pci_write_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS, byte);
+	pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte);
 
 	/*
 	 * Enable hand-instance of the pulse generator and SPI
 	 * controller prefetch of flash.
 	 */
-	byte = pci_read_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL);
+	byte = pci_read_config8(dev, LPC_HOST_CONTROL);
 	byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH;
-	pci_write_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL, byte);
+	pci_write_config8(dev, LPC_HOST_CONTROL, byte);
 
 	cmos_check_update_date();
 
@@ -161,9 +152,8 @@ static void lpc_set_resources(struct device *dev)
 	pci_dev_set_resources(dev);
 }
 
-static void set_child_resource(struct device *child,
-				u32 *reg,
-				u32 *reg_x)
+static void set_child_resource(struct device *dev, struct device *child,
+				u32 *reg, u32 *reg_x)
 {
 	struct resource *res;
 	u32 base, end;
@@ -272,7 +262,7 @@ static void set_child_resource(struct device *child,
 			wideio_index = sb_set_wideio_range(base, res->size);
 			if (wideio_index != WIDEIO_RANGE_ERROR) {
 				/* preserve wide IO related bits. */
-				*reg_x = pci_read_config32(SOC_LPC_DEV,
+				*reg_x = pci_read_config32(dev,
 					LPC_IO_OR_MEM_DECODE_ENABLE);
 
 				printk(BIOS_DEBUG,
@@ -308,11 +298,8 @@ static void lpc_enable_childrens_resources(struct device *dev)
 		for (child = link->children; child;
 		     child = child->sibling) {
 			if (child->enabled
-			    && (child->path.type == DEVICE_PATH_PNP)) {
-				set_child_resource(child,
-						&reg,
-						&reg_x);
-			}
+			    && (child->path.type == DEVICE_PATH_PNP))
+				set_child_resource(dev, child, &reg, &reg_x);
 		}
 	}
 	pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg);