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{gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function 

Use already defined system_reset() and full_reset() functions.

Change-Id: Ic29fab70cf7f23d49c3eeeb97c984c523f973972
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Elyes HAOUAS 2019-05-05 16:29:41 +02:00 committed by Patrick Georgi
parent ba092a9ab6
commit 1bc7b6e135
4 changed files with 10 additions and 17 deletions
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8
src/northbridge/intel/gm45/early_reset.c
View File

@ -16,8 +16,9 @@
#include <types.h> #include <types.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <halt.h>
#include "gm45.h" #include "gm45.h"
void gm45_early_reset(void/*const timings_t *const timings*/) void gm45_early_reset(void/*const timings_t *const timings*/)
@ -63,8 +64,5 @@ void gm45_early_reset(void/*const timings_t *const timings*/)
/* Normally, we would set this after successful raminit. */ /* Normally, we would set this after successful raminit. */
MCHBAR32(DCC_MCHBAR) |= (1 << 19); MCHBAR32(DCC_MCHBAR) |= (1 << 19);
/* Perform system reset through CF9 interface. */ system_reset();
outb(0x02, 0xcf9); /* Set system reset bit. */
outb(0x06, 0xcf9); /* Set CPU reset bit, too. */
halt();
} }

7
src/northbridge/intel/pineview/raminit.c
View File

@ -15,6 +15,7 @@
*/ */
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h> #include <console/console.h>
@ -1744,10 +1745,8 @@ static void sdram_checkreset(void)
} }
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, pmcon3); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, pmcon3);
if (reset) { if (reset)
printk(BIOS_DEBUG, "Power cycle reset...\n"); full_reset();
outb(0xe, 0xcf9);
}
} }
static void sdram_dradrb(struct sysinfo *s) static void sdram_dradrb(struct sysinfo *s)

7
src/northbridge/intel/sandybridge/romstage.c
View File

@ -18,6 +18,7 @@
#include <stdint.h> #include <stdint.h>
#include <console/console.h> #include <console/console.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <timestamp.h> #include <timestamp.h>
@ -47,10 +48,8 @@ void mainboard_romstage_entry(unsigned long bist)
{ {
int s3resume = 0; int s3resume = 0;
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE)
outb(0x6, 0xcf9); system_reset();
halt ();
}
if (bist == 0) if (bist == 0)
enable_lapic(); enable_lapic();

5
src/northbridge/intel/x4x/raminit.c
View File

@ -22,7 +22,6 @@
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <halt.h>
#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ #include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
#else #else
@ -624,9 +623,7 @@ static void checkreset_ddr2(int boot_path)
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2));
printk(BIOS_DEBUG, "Reset...\n"); full_reset();
outb(0xe, 0xcf9);
asm ("hlt");
} }
pmcon2 |= 0x80; pmcon2 |= 0x80;
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);